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C. Gustin

Researcher at Katholieke Universiteit Leuven

Publications -  30
Citations -  661

C. Gustin is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Quantum dot & Dephasing. The author has an hindex of 13, co-authored 30 publications receiving 620 citations. Previous affiliations of C. Gustin include Université catholique de Louvain & IMEC.

Papers
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Journal ArticleDOI

Impact of fin width on digital and analog performances of n-FinFETs

Abstract: This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs ( I – V , C – V and 1/ f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/ f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.
Proceedings ArticleDOI

Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-Roughness

TL;DR: In this paper, the authors compared the performance of resist-and spacer-defined fin-patterned SRAM bit-cells with and without spacer defined fins at VDD = 1.2V.
Journal ArticleDOI

The Potential of FinFETs for Analog and RF Circuit Applications

TL;DR: It is demonstrated with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed.
Journal ArticleDOI

Dwell-time-limited coherence in open quantum dots.

TL;DR: Measurements of the electron phase coherence time tau(varphi) on a wide range of open ballistic quantum dots (QDs) made from InGaAs heterostructures provide new insight into the long-standing problem of the saturation of tau("varphi") in these systems: the dwell time becomes the limiting factor for electron interference effects in QDs at low temperature.