Showing papers by "Charles J. Alpert published in 2010"

New placement prediction and mitigation techniques for local routing congestion

Abstract: Local routing congestion is becoming increasingly important as complex design rules make local pin access the bottle-neck for modern designs and routers. Since congestion analysis based on global routing does not model these effects, routability-driven placement and physical synthesis fail to alleviate local congestion. This work models routing congestion at the placement level in order to apply local congestion mitigation. We propose a local congestion metric that computes a "routing-difficulty" score for every cell in the design library. To disperse local congestion, we apply a suite of detailed placement techniques called MILOR (Movement, cell Inflation and Legalization, and Optimization within a Row). Experimental results show that our techniques can significantly improve routing quality on real industry designs from 65, 45, and 32 nanometer technologies.

What makes a design difficult to route

Abstract: Traditionally, the goal of physical synthesis has been to produce a physical realization of the input netlist that meets its timing constraints with minimum area However, design routability has emerged from a secondary objective to perhaps the primary objective, in no small part due to the myriad of rules and constraints that emerge with each successive technology This work overviews the complexities with modeling congestion during physical synthesis and discusses how optimizations may be able to provide some relief

ITOP: integrating timing optimization within placement

Abstract: Timing-driven placement is a critical step in nanometer-scale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a commonly used technique. This paper shows that such an approach can improve timing, but often degrades wire length and routability. Another problem with existing timing-driven placers is inconsistencies in the definition of timing closure. Approaches using linear programming are forced to make assumptions about the timing models that simplify the problem. To truly do timing-driven placement, the placer must be able to make queries to a real timing analyzer with incremental capabilities. This paper describes an incremental timing-driven placer called ITOP. Using accurate timing from an industrial static timer, ITOP integrates incremental timing closure optimizations like buffering and repowering within placement to improve design timing without degrading wire length and routability.Experimental results on a set of optimized industrial circuit netlists show that ITOP significantly outperforms conventional net-weight based timing-driven placement. In particular, on average, it obtains an improvement of over 47.45%, 9.88% and 5% in the worst slack, total negative slack and wire length as compared to the conventional flow.

Design-hierarchy aware mixed-size placement for routability optimization

Abstract: Routability is a mandatory metric for modern large-scale mixed-size circuit placement which typically needs to handle hundreds of large macros and millions of small standard cells. However, most existing academic mixed-size placers either focus on wirelength minimization alone, or do not consider the impact of movable macros on routing. To remedy these insufficiencies, this paper formulates design-hierarchy information as a novel fence force in an analytical placement framework. Unlike a state-of-the-art routability-driven placer that simply removes net bounding boxes during placement, this paper utilizes two different optimization forces, the global fence force and the local spreading force, to determine the positions of both standard cells and macros. We utilize design-hierarchy information to determine block distributions globally, and locally we add additional spreading forces to preserve sufficient free space among blocks by a net-topology estimation. With the interactions between these two forces, our placer can well balance routability and wirelength. Experimental results show that our placer can achieve the best routability and routing time among all published works.

Detecting tangled logic structures in VLSI netlists

Abstract: This work proposes a new problem of identifying large and tangled logic structures in a synthesized netlist. Large groups of cells that are highly interconnected to each other can often create potential routing hotspots that require special placement constraints. They can also indicate problematic clumps of logic that either require resynthesis to reduce wiring demand or specialized datapath placement. At a glance, this formulation appears similar to conventional circuit clustering, but there are two important distinctions. First, we are interested in finding large groups of cells that represent entire logic structures like adders and decoders, as opposed to clusters with only a handful of cells. Second, we seek to pull out only the structures of interest, instead of assigning every cell to a cluster to reduce problem complexity. This work proposes new metrics for detecting structures based on Rent's rule that, unlike traditional cluster metrics, are able to fairly differentiate between large and small groups of cells. Next, we demonstrate how these metrics can be applied to identify structures in a netlist. Finally, our experiments demonstrate the ability to predict and alleviate routing hotspots on a real industry design using our metrics and method.

Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Abstract: In a complete physical synthesis flow, optimization transforms, that can improve the timing on critical paths that are already well-optimized by a series of powerful transforms (timing driven placement, buffering and gate sizing) are invaluable. Finding such a transform is quite challenging, to say nothing of efficiency. This work explores innovative cloning (gate duplication) techniques to improve timing-closure in a physical synthesis environment.With a buffer-aware interconnect timing model, new polynomial-time optimal algorithms are proposed for timing-driven cloning, including both finding optimal sink partitions (identifying the fan-outs) for the original and the duplicated gates, as well as physical locations for both gates. In particular, we present an O(m)-time optimal algorithm to minimize the worst slack if the original gate is movable, and an O(m log m) algorithm if the original gate is fixed, where $m$ is the number of fan-outs. To the best of our knowledge, this work is the first one considering the timing-driven cloning problem under a buffer-aware interconnect delay model.For a hundred testcases in 45nm technology node, we demonstrate significant timing improvement due to our cloning techniques as compared to other existing timing-optimization transforms. Extensions to other factors, such as wirelength, FOM and placement obstacles are further discussed.

Speeding Up Physical Synthesis with Transactional Timing Analysis

Abstract: Modern physical-synthesis flows operate on very large designs and perform increasingly aggressive timing optimizations. Traditional incremental timing analysis now represents the single greatest bottleneck in such optimizations and lacks the features necessary to support them efficiently. This article describes a paradigm of transactional timing analysis, which, together with incremental updates, offers an efficient, nested undo functionality that avoids significant timing calculations.

Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs

Abstract: A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is rentable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.

Multiple threshold voltage cell families based integrated circuit design

Abstract: A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families.

Method and system for providing slew constrained minimum cost buffering

Abstract: A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew arc added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution.