Proceedings ArticleDOI
What makes a design difficult to route
Charles J. Alpert,Zhuo Li,Michael D. Moffitt,Gi-Joon Nam,Jarrod A. Roy,Gustavo E. Tellez +5 more
- pp 7-12
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This work overviews the complexities with modeling congestion during physical synthesis and discusses how optimizations may be able to provide some relief.Abstract:
Traditionally, the goal of physical synthesis has been to produce a physical realization of the input netlist that meets its timing constraints with minimum area However, design routability has emerged from a secondary objective to perhaps the primary objective, in no small part due to the myriad of rules and constraints that emerge with each successive technology This work overviews the complexities with modeling congestion during physical synthesis and discusses how optimizations may be able to provide some reliefread more
Citations
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Proceedings ArticleDOI
The ISPD-2011 routability-driven placement contest and benchmark suite
TL;DR: The ISPD-2011 routability-driven placement contest and the associated benchmark suite are described, and a new benchmark suite that is being released in conjunction with the contest is described, which can be used to perform both placement and global routing.
Journal ArticleDOI
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement
TL;DR: RePlAce is the first work to achieve superior solution quality across all the IS PD-2005, ISPD-2006, MMS, DAC-2012, and ICCAD-2012 benchmark suites with a single global placement engine.
Proceedings ArticleDOI
The DAC 2012 routability-driven placement contest and benchmark suite
TL;DR: The aim of the DAC 2012 routability-driven placement contest is to release challenging benchmark designs that are derived from modern industrial ASICs, and contain information to perform both placement and routing, and present a new congestion metric, as well as an accurate congestion analysis framework to evaluate and compare the routability of various placement algorithms.
Proceedings ArticleDOI
A SimPLR method for routability-driven placement
TL;DR: Lookahead routing is developed to give the placer advance, firsthand knowledge of trouble spots, not distorted by crude congestion models, and global placement is extended to spread cells apart in congested areas, and move cells together in less-congested areas to ensure short, routable interconnects and moderate runtime.
Proceedings ArticleDOI
Progress and challenges in VLSI placement research
TL;DR: The history of placement research, the progress leading up to the state of the art, and outstanding challenges are surveyed.
References
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BookDOI
Handbook of Algorithms for Physical Design Automation
TL;DR: Handbook of Algorithms for Physical Design Automation provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade.
Proceedings ArticleDOI
An effective congestion driven placement framework
Ulrich Brenner,André Rohe +1 more
TL;DR: A fast but reliable way to detect routing criticalities in VLSI chips by using a congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm.
Proceedings ArticleDOI
Routability driven white space allocation for fixed-die standard-cell placement
TL;DR: A white space allocation approach that dynamically assigns white space according to the congestion distribution of the placement, combined with a multilevel placement flow, significantly improves placement routability and layout quality.
Journal ArticleDOI
Routability-Driven Placement and White Space Allocation
TL;DR: A congestion-driven placement flow that considers in the global placement stage the routing demand to replace cells in order to avoid congested regions and allocates appropriate amounts of white space into different regions of the chip according to the congestion map.
Proceedings ArticleDOI
ISPD 2006 Placement Contest: Benchmark Suite and Results
TL;DR: This talk introduces the new suite of ISPD 2006 placement benchmarks, which are all directly derived from real industrial ASIC designs and represent today's mixed-size physical design constraints in terms of size and complexity.