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Charles J. Alpert
Researcher at IBM
Publications - 224
Citations - 8576
Charles J. Alpert is an academic researcher from IBM. The author has contributed to research in topics: Routing (electronic design automation) & Timing closure. The author has an hindex of 49, co-authored 224 publications receiving 8287 citations. Previous affiliations of Charles J. Alpert include Cadence Design Systems & University of Minnesota.
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Patent
Routing and timing using layer ranges
TL;DR: In this paper, a method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments.
Journal ArticleDOI
Techniques for scalable and effective routability evaluation
Yaoguang Wei,Cliff Sze,Natarajan Viswanathan,Zhuo Li,Charles J. Alpert,Lakshmi Reddy,Andrew D. Huber,Gustavo E. Tellez,Douglas Keller,Sachin S. Sapatnekar +9 more
TL;DR: This article proposes three approaches to model local routing resources and proposes a smoothing technique to reduce the number of noisy hotspots and obtain a more accurate routability evaluation result and develops a new metric which represents congestion maps with higher fidelity.
Journal ArticleDOI
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment
TL;DR: This work presents the first theoretical advance for the timing-driven minimum cost layer assignment problem, and can approximate the optimal layer assignment solution by a factor of 1 + isin in O(m log log M ldrn 3 isin2) time.
Proceedings ArticleDOI
Partitioning with terminals: a “new” problem and new benchmarks
TL;DR: This paper empirically shows that with fixed terminals in the instance, less effort is needed to stably reach a given solution quality, and develops new benchmark formats that flexibly capture the presence of terminals and any geometric embedding information associated with the partitioning instance.
Journal ArticleDOI
Path-Based Buffer Insertion
TL;DR: Experimental results show that the proposed novel path-based-buffer-insertion (PBBI) scheme can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net-based approaches.