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Charles J. Alpert
Researcher at IBM
Publications - 224
Citations - 8576
Charles J. Alpert is an academic researcher from IBM. The author has contributed to research in topics: Routing (electronic design automation) & Timing closure. The author has an hindex of 49, co-authored 224 publications receiving 8287 citations. Previous affiliations of Charles J. Alpert include Cadence Design Systems & University of Minnesota.
Papers
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Patent
Incremental timing-driven, physical-synthesis using discrete optimization
TL;DR: In this paper, the placement of logic gates of a subcircuit in a physical synthesis flow is optimized using a path smoothing utility, which identifies one or more movable gates based on at least one selection criteria.
Proceedings ArticleDOI
Datapath routing based on a decongestion metric
TL;DR: An algorithm that considers all the nets simultaneously within a four-layer datapath routing environment and achieves significant routability within a small number of available tracks is presented.
Journal ArticleDOI
Speeding Up Physical Synthesis with Transactional Timing Analysis
TL;DR: This article describes a paradigm of transactional timing analysis, which, together with incremental updates, offers an efficient, nested undo functionality that avoids significant timing calculations.
Journal ArticleDOI
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement
Charles J. Alpert,Andrew Caldwell,Tony F. Chan,Dennis J.-H. Huang,Andrew B. Kahng,Igor L. Markov,M. S. Moroz +6 more
TL;DR: The focus of this investigation is the coupling of numerical solvers to iterative partitioners that is a hallmark of the quadratic placement methodology, and it is shown that a modern multilevel FM implementation derives no benefit from such coupling.
Patent
Boundary latch and logic placement to satisfy timing constraints
Charles J. Alpert,Mark D. Aubel,Gregory Ford,Zhuo Li,Chin Ngai Sze,Paul G. Villarrubia,Natarajan Viswanathan +6 more
TL;DR: In this article, a subset of boundary latches in an integrated circuit are designated using a depth-first search to identify the first latch along interconnection paths with the PI/PO, and filtering out ineligible latch according to designer rules.