A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.

Cut-mask patterning process for fin-like field effect transistor (FinFET) device

Vertical integration of two-dimensional van der Waals materials is predicted to lead to novel electronic and optical properties not found in the constituent layers. Here, we present the direct synthesis of two unique, atomically thin, multi-junction heterostructures by combining graphene with the monolayer transition-metal dichalcogenides: molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2) and tungsten diselenide (WSe2). The realization of MoS2-WSe2-graphene and WSe2-MoS2-graphene heterostructures leads to resonant tunnelling in an atomically thin stack with spectrally narrow, room temperature negative differential resistance characteristics.

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Atomically thin resonant tunnel diodes built from synthetic van der Waals heterostructures

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.

The era of hyper-scaling in electronics

A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

Finfet devices with unique fin shape and the fabrication thereof

A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

Semiconductor fin isolation by a well trapping fin portion

An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.

Semiconductor structures and methods with high mobility and high energy bandgap materials

A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.

Method of Forming CMOS FinFET Device

We present a detailed study on fabrication and characterization of Ge/GeSn heterojunction p-type tunnel-field-effect-transistors (TFETs). Critical process modules as high-k stack and p-i-n diodes are addressed individually. As a result an ultrathin equivalent oxide thickness of 0.84 nm with an accumulation capacitance of $3~\mu \text{F}$ /cm2 was achieved on an extremely scaled tri-layer stack of GeSnOx/Al2O3/HfO2 deposited by atomic-layer deposition monitored in situ by spectroscopic ellipsometry. Combining these process modules, Ge/GeSn heterojunction pTFETs are fabricated and characterized to demonstrate the best in-class pTFET performance in the GeSn material system. The transfer characteristics of the TFETs show signatures of the trap-assisted thermal generation in the subthreshold regime which is explained by a modified Shockley–Read–Hall model. For the ON-state current, we used band-to-band tunneling models calculated using parameters from the density functional theory. We then use the calibrated model to project performance of GeSn pTFETs with increased Sn content (lower bandgap), reduced trap density and ultrathin body geometry. Both experimental and projected results are benchmarked against state-of-the art III–V (e.g., In0.65Ga0.35/GaAs0.4Sb0.6) pTFETs. We demonstrate the ability of GeSn to achieve superior performance with both high ON-current and sub-60mV/decade switching benefiting from the small and direct bandgap for higher Sn contents.

Fabrication, Characterization, and Analysis of Ge/GeSn Heterojunction p-Type Tunnel Transistors

Metallic diffusion through high-K HfO2, caused by high temperature metal-nitride decomposition, was reduced by using robust HfAlON. Useful dual effective work-function (phim,eff) of 4.25 and 5.15 eV are obtained in TaTb0.2N/HflON and Ir/HfAlON at 1.7 nm EOT. Good dual phim,eff of 4.15 and 4.9 eV are also obtained in YbxSi/HfAlON and IrxSi/HfAlON FUSI-gates by reduced metal diffusion at lower temperature

Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference

A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed An exemplary CMOS FinFET device includes a substrate including a first region and a second region The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin

Cheng-Hsien Wu

Papers

Semiconductor structures and methods with high mobility and high energy bandgap materials

Method of Forming CMOS FinFET Device

Fabrication, Characterization, and Analysis of Ge/GeSn Heterojunction p-Type Tunnel Transistors

Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference

A cmos finfet device and a method of forming the cmos finfet device