Showing papers by "Chenming Hu published in 1988"

Simulation of MOSFET lifetime under AC hot-electron stress

Abstract: A substrate current model and a quasistatic hot-electron-induced MOSFET degradation model have been implemented using the Substrate Current And Lifetime Evaluator (SCALE) package. It is shown that quasistatic simulation is valid for a class of waveforms that includes those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and postprocessor fashion to form an independent simulator. The preprocessor interprets the input deck and requests SPICE to output the transient node voltages of the user-selected devices. The postprocessor then calculates the transient substrate current and makes a lifetime prediction. >

Circuit aging simulator (CAS)

Abstract: A circuit aging simulator (CAS) has been developed as part of the BSIM (Berkeley Short-channel Igfet Model) family to predict the effects of hot-electron degradation on MOS circuit behavior Using the SPICE2 of SPICE 3 circuit simulator in a UNIX environment, CAS simulates circuit behavior at a user-specified future time using fresh and DC prestressed BSIM parameter process files CAS is configured in a pre- and postprocessor configuration, so that no modifications to the SPICE code are necessary Iterative simulation to take into account ongoing degradation can also be done through an accompanying UNIX shell scrip program >

Statistical modeling of silicon dioxide reliability

Abstract: A technique is presented for predicting lifetime of an oxide to different voltages, different oxide areas and different temperatures. Using the defect density model in which defects are modelled as effective oxide thinning, many reliability parameters such as yield, failure rate, and screen time/screen yield can be predicted. Effects of oxide thickness, process improvements including defect gettering, and alternative dielectrics such as CVD oxides are evaluated in terms of defect density as a function of effective oxide thinning. >

Polarity asymmetry of oxides grown on polycrystalline silicon

Abstract: The quality of oxide thermally grown on polycrystalline silicon, commonly referred to as polyoxide, is strongly dependent on polysilicon doping processes and polyoxide growth conditions. The electrical properties of polyoxides using different polysilicon doping processes (in situ, ion implanted, and POCl/sub 3/) and different oxidation processes (dry, wet, and LPCVD) have been studied. The emphasis is on the dependence of the polarity asymmetry of leakage current, critical electric field histogram, electron trapping rate, and charge to breakdown. Polyoxides with in situ doped polysilicon exhibit an unusual polarity asymmetry, i.e. higher field enhancement and charge to breakdown are observed when the upper electrode is biased negative. This is the opposite of the asymmetry reported for polyoxides before. High-temperature annealing of the polysilicon films prior to oxidation reduces this asymmetry. >

Determination of carrier lifetime from rectifier ramp recovery waveform

Abstract: A charge-control analysis is used to obtain an expression relating the carrier lifetime to the realistic ramp recovery waveform of a p-i-n diode of arbitrary softness. The method is shown to produce a consistent lifetime for different values of forward currents, current ramp rates, and the resultant softness factors. >

Recovery of threshold voltage after hot-carrier stressing

Abstract: The recovery of threshold voltage due to high drain or gate voltage and the effects of hot-carrier stressing on the drain breakdown voltage of MOSFETs have been studied. A high oxide field causes slow recovery through tunneling detrapping of electrons in both p- and n-MOSFETs. For n-MOSFETs the mechanism of fast recovery is low-level hole injection at high V/sub D/. Hot-carrier stressing at high V/sub G/ causes the drain breakdown voltage to decrease (walk-in). This results in enhanced hold injection, thus increasing the rate of subsequent recovery of V/sub t/. The breakdown voltage increases and then decreases when stressed at low gate voltages. >

Hot-electron currents in deep-submicrometer MOSFETs

Abstract: A comprehensive study of hot-electron-induced substrate and gate currents in deep-submicrometer MOSFETs is presented. The substrate- and gate-current characteristics for devices with channel lengths as small as 0.2 mu m and oxide thickness as thin as 55 AA are examined. Implications for MOSFET reliability and EPROM programming are discussed. In the deep-submicrometer regime, established hot-electron concepts and models are found to be applicable; however, consideration of the finite depth of the current path and current-crowding-induced weak gain control becomes much more important. With these modifications, physical analytical models for substrate and gate currents are developed and verified for deep-submicrometer devices. >

The effect of channel hot carrier stressing on gate oxide integrity in MOSFET

Abstract: The correlation between channel hot carrier stressing and gate oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate oxide integrity even when other parameters (e.g., Delta V/sub T/ and Delta VI/sub D/) have become intolerably degraded. In the extreme cases of stressing at V/sub G/ approximately=V/sub T/ with measurable hole injection current, however, the oxide charge-to-breakdown decreases linearly with the amount of hole fluence injected during the channel hot hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an electrostatic-discharge failure mechanism. >

Flicker noise characteristics of advanced MOS technologies

Abstract: The flicker noise behavior of MOSFETs fabricated by different technologies were characterized. It was found that the technology has very significant effects on the noise characteristics and that all the results can be explained within a unified framework with an oxide trap density distribution. Hot-carrier stressing of n-channel MOSFETs can result in a very large increase of flicker noise, whereas for p-channel MOSFETs the noise is hardly affected. Random telegraph noise is observed in some deep-submicron MOSFETs with very small channel area. A detailed analysis of the telegraph noise suggests that the mobility fluctuation induced by charge trapping plays an important role in the origin of the flicker noise. A novel flicker-noise model incorporating both carrier number and mobility fluctuations is proposed. >

Projecting the minimum acceptable oxide thickness for time-dependent dielectric breakdown

Abstract: A technique is presented for determining the thinnest oxide which satisfies a given time-dependent dielectric breakdown reliability specification. The intrinsic limit for a 10-yr lifetime at 125 degrees C is estimated to be 80 A for 5.5-V operation and 50 A for 3.6-V operation. For the particular technology studies here, 150-AA oxide meets typical reliability specifications for 5.5-V operation, and 80-AA oxide is acceptable for 3.6-V operation (both at 125 degrees C). >

Electrical characteristics of MOSFETs using low-pressure chemical-vapor-deposited oxide

Abstract: The electrical characteristics of MOSFETs and MOS capacitors utilizing thin (80-230 AA) low-pressure chemical-vapor-deposited (LPCVD) oxide films deposited at 12 AA/min are presented. MOSFETs using CVD oxides show good electrical characteristics with 70-90% of the surface mobility of conventional MOSFETs. The CVD oxides exhibit the same low leakage current and high breakdown fields as the thermal oxides, and significantly lower trapping and trap generation rates than thermally grown oxides. Interface state densities of >

Hot-carrier-induced degradation in p-MOSFETs under AC stress

Abstract: Lifetimes under AC stress are calculated with a quasistatic model using parameters extracted from DC stress data. For inverter-like waveforms, the measurement data show reasonable agreement with the simulation results. For waveforms with turnoff transient occurring in the presence of high drain voltage, more degradation than the model predicts is found if the transient is short ( >

Simulation and modeling for soft recovery of p-i-n rectifiers

Abstract: Soft recovery of fast-switching p-i-n rectifiers is studied using experimental data and a novel coupled device and circuit simulator An analytical model for determining lifetimes is presented and verified by numerical simulations The softness factor is difficult to model analytically; hence simulations are necessary Coupled device and circuit simulations also allow a determination of the magnitude of the inductive voltage spike that appears across the rectifier during an unclamped reverse recovery >

Characteristics of CMOS devices in high-energy boron-implanted substrates

Abstract: CMOS devices on substrates subject to high-energy implantation of boron for buried-layer fabrication are examined. FET device characteristics, threshold voltage, and breakdown characteristics are investigated, along with mobility and minority-carrier lifetime. In addition, well leakage and breakdown are studied in an effort to provide guidelines for well design in an megaelectronvolt-implanted substrate. It is seen that MOSFET transistor characteristics are virtually unaffected by the implant. Latchup behavior improves with the incorporation of the buried layer, and the holding voltage increases as the well and implant depths decrease. >

A charge-conserving non-quasistatic MOSFET model for SPICE transient analysis

Abstract: An analytic charge-conserving nonquasistatic (NQS) model has been derived for long-channel MOSFETs and implemented in SPICE3. It is based on an approximate solution to the current-continuity equation. Comparison has been made among this model, the numerical solution to the 1-D current-continuity equation, and the quasistatic (QS) SPICE models. The charge injection at the turnoff transient of a NMOS switch has been simulated using this model and conventional QS models, and it has been found that the QS models give inaccurate results even for the moderately short channel (3- mu m) MOSFETs when the input voltage is changing at the moment of turnoff. A differential sample-hold circuit has also been simulated using this model, and the results are compared with those from QS models. The CPU time using this model is around 3 to 4 times longer than for the conventional QS SPICE models. >

Effects of high current pulses on integrated circuit metallization reliability

Abstract: Transient heat flow analysis using two-dimensional finite-element method has been used to calculate the temperature rise of aluminum lines on passivated and unpassivated silicon substrates. The results are used to predict the effect of self-heating on the electromigration lifetime of aluminum interconnects under pulse current stressing. A model has been developed to incorporate damage relaxation and self-heating effects on electromigration. It is shown that self-heating is expected to produce less than 20% error in typical accelerated testing conditions provided the peak current density (J/sub p/) is less than 4*10/sup 6/ A/cm/sup 2/. Design rules based on keeping the average current density (J/sub av/) constant are acceptable provided that duty factor is larger than 1% for all frequencies above 1 MHz. >

Oxides grown on textured single-crystal silicon for enhanced conduction

Abstract: The electrical properties and integrity of oxides grown on textured single‐crystal silicon (TSC oxides) are investigated and are compared to oxides grown on untextured single‐crystal silicon (normal oxides) and oxides grown on polycrystalline silicon (polyoxides) The 230 A TSC oxide exhibited enhanced electron injection in both polarities, reducing the voltage necessary for JG=+1 mA/cm2 from 21 V for normal 230 A oxides to 5 V This made the 230 A TSC oxide approximately equivalent to a 60 A normal oxide The electron trapping rate for the TSC oxide was similar to that of 230 A normal oxides but is much smaller than that of polyoxides Charge‐to‐breakdown (QBD) measurements showed a much better QBD histogram (large area capacitors) for the TSC oxide than for 230 A and 60 A normal oxides

Electrical Characteristics of MOSFET's Using Low-Pressure Chemical-Vapor-Deposited

Abstract: This paper presents the electrical characteristics of MOS- FET's and MOS capacitors utilizing thin (80-230 A) low-pressure chemical-vapor-deposited oxide films deposited at 12 A/min. MOS- FET's using CVD oxides show good electrical characteristics with 70-90 percent of the surface mobility of conventional MOSFET's. The CVD oxides exhibit the same low leakage current and high breakdown fields as the thermal oxides, and significantly lower trapping and trap generation rates than thermally grown oxides. Interface state densities of s3 x 1Olo cm-*.eV-' are obtained from CVD devices by using a short annealing in oxygen ambient following the deposition. These results indicate that these LPCVD oxide films may be promising dielectrics for MOS device application.

Localized interface trap generation in SILO-isolated MOSFETs during PECVD nitride passivation

Abstract: The authors report the generation of interface traps during the plasma-enhanced chemical vapor deposition of silicon nitride passivation in MOS structures that utilize a sealed-interface local oxidation scheme (SILO) for device isolation. These traps are highly localized at the boundaries between gate and field oxides, causing enhanced subthreshold conduction. Localized interface traps of this type were not observed in identical MOS structures that use conventional LOCOS (local oxidation of silicon) isolation and were eliminated by thermal anneals at 450 degrees C. Anneals in hydrogen ambients resulted in enhanced rates of hot-carrier-induced degradation. The high densities and localized nature of these anomalous traps make possible a novel mode of device operation in which source-drain conduction is strongly modulated by substrate bias. >

Hot-carrier effects in polysilicon emitter bipolar transistors

Abstract: The degradation of self-aligned, polysilicon emitter transistors is described for a wide range of constant current stress on several device sizes. The experimental results indicate that Delta I/sub B/ can be expressed as AQ/sup n/, with n=0.5 for these devices. Except for large values of I/sub R/, A varies in a power-lay fashion with I/sub R/. The dependence of Delta I/sub B/ upon the forward current at which the device is operating can be expressed as A=BJ/sup gamma //sub C/. It is observed that n is characteristic of all devices and stress currents, B is constant for a given device size, and gamma varies with device size and reverse current. >

Effect of Hydrogen on Thermal Stress in Layered Structure of Ti and Ti(Al) Thin Films.

Abstract: The effect of hydrogen on stress in thin film structures has been investigated for Ti, Al, Ti(Al) and Al(Ti) films. The stress in the metal films was measured in-situ as a function of temperature and ambient (vacuum of 10 -6 Torr., forming gas and nitrogen) using a bending beam technique. The metal films were deposited on fused quartz or polyimide/fused quartz substrates using a dual e-gun evaporation method. The stress in pure Ti films was found to be strongly dependent on the annealing environment. Upon thermal cycling in a forming gas, an abrupt change of stress in the Ti film due to crack formation and delamination in the Ti film was observed. The possibility to eliminate the hydrogen effect by Al addition has been investigated. The hydrogen effect can be reduced by an addition of 5 at.% Al, but stress induced crack formation similar to the pure Ti film was still observed in this alloy film. An increase to 20 at.% Al in the alloy films eliminated the hydrogen effect, however, such an alloy film was brittle as cracks and delamination were observed after one thermal cycle from room temperature to 350 °C. A similar behavior in stress relaxation was observed in an Al-riched film with 20 at.% Ti.