Y
Yu-Jun Chou
Researcher at National Tsing Hua University
Publications - 4
Citations - 57
Yu-Jun Chou is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: Leakage (electronics) & Gate dielectric. The author has an hindex of 3, co-authored 4 publications receiving 56 citations.
Papers
More filters
Proceedings ArticleDOI
Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography
Hou-Yu Chen,Chang-Yun Chang,Chien-Chao Huang,Tang-Xuan Chung,Sheng-Da Liu,Jiunn-Ren HwangYi-Hsuan Liu,Yu-Jun Chou,Hong-Jang Wu,King-Chang Shu,Chung-Kan Huang,Jan-Wen You,Jaw-Jung Shin,Chun-Kuang Chen,Chia-Hui Lin,Ju-Wang Hsu,Bao-Chin Perng,Pang-Yen Tsai,Chi-Chun Chen,Jyu-Horng Shieh,Han-Jan Tao,Shin-Chang Chen,Tsai-Sheng Gau,Fu-Liang Yang +22 more
TL;DR: In this article, a hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm SiON gate dielectric has been developed for advanced SOC applications.
Proceedings ArticleDOI
A 65nm node strained SOI technology with slim spacer
Fu-Liang Yang,Chien-Chao Huang,Hou-Yu Chen,Jhon-Jhy Liaw,Tang-Xuan Chung,Hung-Wei Chen,Chang-Yun Chang,Cheng Chuan Huang,Kuang-Hsin Chen,Di-Hong Lee,Hsun-Chih Tsao,Cheng-Kuo Wen,Shui-Ming Cheng,Yi-Ming Sheu,Ke-Wei Su,Chi-Chun Chen,Tze-Liang Lee,Shih-Chang Chen,C.H. Chen,Cheng-hung Chang,Jhi-cheng Lu,W. Chang,Chuan-Ping Hou,Ying-Ho Chen,Kuei-Shun Chen,Ming Lu,Li-Wei Kung,Yu-Jun Chou,Fu-Jye Liang,Jan-Wen You,King-Chang Shu,Bin-Chang Chang,Jaw-Jung Shin,Chun-Kuang Chen,Tsai-Sheng Gau,Bor-Wen Chan,Yi-Chun Huang,Han-Jan Tao,J.H. Chen,Yung-Shun Chen,Yee-Chia Yeo,Samuel Fung,Carlos H. Diaz,Chii-Ming Wu,Burn-Jeng Lin,Liang Min-Chang,J.Y.-C. Sun,Chenming Hu +47 more
TL;DR: In this article, a 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A/A//spl µ/m for N-FETs and P-Fet, respectively, at an off-state leakage of 40 nA/spl μ/m using 1 V operation.
Proceedings ArticleDOI
45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell
Fu-Liang Yang,Cheng-Chuan Huang,Chien-Chao Huang,Tang-Xuan Chung,Hou-Yu Chen,Chang-Yun Chang,Hung-Wei Chen,Di-Hong Lee,Sheng-Da Liu,Kuang-Hsin Chen,Cheng-Kuo Wen,Shui-Ming Cheng,Chang-Ta Yang,Li-Wei Kung,Chiu-Lien Lee,Yu-Jun Chou,Fu-Jye Liang,Lin-Hung Shiu,Jan-Wen You,King-Chang Shu,Bin-Chang Chang,Jaw-Jung Shin,Chun-Kuang Chen,Tsai-Sheng Gau,Ping-Wei Wang,Bor-Wen Chan,Peng-Fu Hsu,Jyu-Honig Shieh,Samuel Fung,Carlos H. Diaz,Chii-Ming Wu,Yee-Chaung See,Burn-Jeng Lin,M.S. Liang,J.Y.-C. Sun,Chenming Hu +35 more
TL;DR: The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation as discussed by the authors.
Proceedings ArticleDOI
High sensitivity DNA sieving technology by entropic trapping in 3D artificial nano-channel matrices
Chung-Hsuan Wang,Cho-Lun Hsu,Wen-Cheng Chiu,Tung-Yen Lai,Tong-Huan Chou,Ivy Yang,ChiaHua Ho,Chenming Hu,Fu-Liang Yang,Yu-Jun Chou +9 more
TL;DR: In this paper, a mechanism based on entropic trapping is proposed for the observed high DNA sieving sensitivity by 3D artificial nano-channel matrices, which is based on proven NEMS, MEMS and Through-Si-Via (TSV) technologies and offers high potential for application in portable bioelectronic instruments.