An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Improving resolution in photolithography with a phase-shifting mask

A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.

Pattern inspection apparatus and method

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Dynamic array architecture

A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.

Technology migration for integrated circuits with radical design restrictions

A method is provided for reducing Critical Dimension (CD) non-uniformity in creating a patterned layer of semiconductor material. Two masking layers are respectively created, the first masking layer comprising a main pattern, an isolated pattern and a dummy pattern, the second masking layer exposing the dummy pattern. Methods of compensating for optical proximity effects and micro-loading, as provided by the invention, are applied in creating the first masking layer. The patterned first masking layer is transposed to an underlying layer creating a first pattern therein. The second masking layer removes the dummy features from the transposed first pattern, creating a second pattern therein comprising a main pattern and an isolated pattern to which compensation for optical proximity effects and micro-loading have been applied. The second pattern serves for additional etching of underlying semiconductor material.

New method to reduce CD non-uniformity in IC manufacturing

A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended.

Devices and methods for improved reflective electron beam lithography

A method for splitting a pattern layout including providing the pattern layout having features, checking the pattern layout to determine the features that require splitting, coloring the features that require splitting with a first and second color, resolving coloring conflicts by decomposing the feature with the coloring conflict and coloring the decomposed feature with the first and second color, and generating a first mask with features of the first color and a second mask with features of the second color.

Method and system for a pattern layout split

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current

Jaw-Jung Shin

Papers

New method to reduce CD non-uniformity in IC manufacturing

Devices and methods for improved reflective electron beam lithography

Method and system for a pattern layout split

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

A 65nm node strained SOI technology with slim spacer