There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Monte Carlo simulations have been widely used by microscopists for the last few decades. In the beginning it was a tedious and slow process, requiring a high level of computer skills from users and long computational times. Recent progress in the microelectronics industry now provides researchers with affordable desktop computers with clock rates greater than 3 GHz. With this type of computing power routinely available, Monte Carlo simulation is no longer an exclusive or long (overnight) process. The aim of this paper is to present a new user-friendly simulation program based on the earlier CASINO Monte Carlo program. The intent of this software is to assist scanning electron microscope users in interpretation of imaging and microanalysis and also with more advanced procedures including electron-beam lithography. This version uses a new architecture that provides results twice as quickly. This program is freely available to the scientific community and can be downloaded from the website: (www.gel.usherb.ca/casino).

/pdf/casino-v2-42-a-fast-and-easy-to-use-modeling-tool-for-4x80ysvonj.pdf

CASINO V2.42: a fast and easy-to-use modeling tool for scanning electron microscopy and microanalysis users.

Current integration, architectural design and manufacturing technologies are not suited for the computing density and power efficiency requested by Exascale computing. New approaches in hardware architecture are thus needed to overcome the technological barriers preventing the transition to the Exascale era. In that scope, we report successful fabrication of first ExaNoDe's MCM prototypes dedicated to Exascale computing applications. Each MCM was composed of 2 Xilinx Zynq Ultrascale+ MPSoC, assembled on advanced 68.5 mm x 55 mm laminate substrates specifically designed and fabricated for the project. Acoustic microscopy, x-ray, cross-section and Thermo-Moire investigations revealed no voids, shorts, delamination, cracks or warpage issues. Two MCMs were mounted on a daughter board by FORTH for testing purposes. The DDR memories on the 4 SODIMMs of the daughter board were successfully tested by running extensive Xilinx memory tests with clock frequencies of 1866 MHz and 2133 MHz. All 4 FPGAs were programmed with the Xilinx integrated bit error ratio test (IBERT) tailored for this board for links testing. All intra-board high-speed links between all FPGAs were stable at 10 Gbps, even under the more demanding 31-bit PRBS (Pseudorandom Binary Sequence) tests.

FPGA-based Multi-Chip Module for High-Performance Computing

In this paper, we demonstrate electron beam lithography at energies ranging from 2 keV to 100 keV, on sub-100 nm thick 
resists. Such uniform and thin electron beam sensitive films can be deposited by evaporation or by plasma deposition. 
Two examples of such resists are studied, QSR-5 which is a negative sterol based evaporated resist and QPR-P50 which 
is a positive PECVD deposited fluoropolymer resist. AFM measurements demonstrate surface roughness smaller then 
3 nm for QSR-5 and 0.7 nm for QPR-P50. In both cases, 50 nm features or better are patterned using electron beam 
lithography on a template blank consisting of a glass substrate, coated with a 10 nm thick Cr transfer layer and a resist 
layer. LER (3σ) is measured to be less then 8% for 50 nm wide lines in QSR-5 and of approx. 10% for 50 nm wide lines 
in QPR-P50.

Plasma deposited and evaporated thin resists for template fabrication

Spray coating of Ba0.6Sr0.4TiO3 nanoparticles: a low-cost and scalable process for the deposition of dielectric thin films

https://robots.iopscience.iop.org/article/10.1088/1361-6528/abb301/pdf

Erratum: Conductive filament evolution dynamics revealed by cryogenic (1.5 K) multilevel switching of CMOS-compatible Al2O3/TiO2 resistive memories (2020 Nanotechnology 31 445205)

Dominique Drouin

Papers

FPGA-based Multi-Chip Module for High-Performance Computing

Plasma deposited and evaporated thin resists for template fabrication

Spray coating of Ba0.6Sr0.4TiO3 nanoparticles: a low-cost and scalable process for the deposition of dielectric thin films

Erratum: Conductive filament evolution dynamics revealed by cryogenic (1.5 K) multilevel switching of CMOS-compatible Al2O3/TiO2 resistive memories (2020 Nanotechnology 31 445205)

Contributions à l'avancement de techniques de caractérisation de semiconducteur au microscope électronique à balayage