Showing papers by "Eric Beyne published in 2000"

Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device

Abstract: The present invention provides a method of transfer of a first planar substrate with two major surfaces to a second substrate, comprising the steps of: forming the first planar substrate, attaching one of the major surfaces of the first planar substrate to a carrier by means of a release layer; attaching the other major surface of the first substrate to the second substrate with a curable polymer adhesive layer; partly curing the polymer adhesive layer, disconnecting the release layer from the first substrate to separate the first substrate from the camer, followed by coing the polymer adhesive layer.

Image sensor ball grid array package and the fabrication thereof

Abstract: The present invention is related to an image sensor packaging technique based on a Ball Grid Array (BGA) IC packaging technique, further referred to as image sensor ball grid array (ISBGA). A transparent cover is attached to a semiconductor substrate. Depending on the method of attaching the cover to the substrate a hermetic or non-hermitic sealing is obtained. The obtained structure can be connected trough wire-bonding or flip chip connection.

The indent reflow sealing (IRS) technique-a method for the fabrication of sealed cavities for MEMS devices

Abstract: A variety of microelectromechanical system devices requires encapsulation of their crucial fragile parts in a hermetically sealed cavity for reasons of protection Hermeticity of the cavity and controllability of the ambient (gas pressure and gas composition) can be critical to the device performance In order to minimize damage during handling, the cavity is preferably realized at the same time the device is fabricated, ie, at wafer level This paper reports the development of a hermetic packaging technique satisfying all the above The method is referred to as the indent-reflow-sealing (IRS) technique, which relies on a multiple-chip fluxless solder-based joining technique and seal Key process steps are the creation of an indent in the solder, the plasma pretreatment of the bonding surfaces, the pre-bonding (or sticking) of the chips and, the closing of the indent during a low-temperature (220/spl deg/C-350/spl deg/C) solder reflow in a clean controlled ambient using a designated oven As opposed to other methods, the IRS method allows a greater flexibility with respect to the choice of the sealing gas and pressure, thereby offering a very hermetic seal and compatibility with low-cost high-throughput batch fabrication techniques Flip-chip assemblies based on SnPb (67/37) solder and Au as the top surface metallization, have been reflowed in a forming gas ambient and have next been characterized on shear strength, hermeticity, and susceptibility to thermal stresses The method has been successfully implemented in the process flow of an electromagnetic microrelay for the realization of the cavity housing the electrical contacts

Electrodeposition for the synthesis of microsystems

Abstract: Electroplating is an emerging technique for the production of microsystems. This is due to advantages such as high rate of deposition, high resolution, high shape fidelity, simple scalability, and good compatibility with existing processes in microelectronics. Materials ranging from high-conductivity metals over soldering connections to ferromagnets can be deposited. In this paper the basics of electroplating are reviewed and examples of recent applications of electroplating in the processing of microsystems are presented.

Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques

Abstract: The bond pad design on a chip can be reconfigured to a new pad design using a redistribution layer, based on multichip module-deposited (MCM-D) technology. The new pad configuration can be used for flip chip mounting. The thermo-mechanical reliability of these redistributed flip chip structures is in particular determined by the visco-plastic deformations of the solder joints and by the stresses in the photosensitive BCB redistribution layers. In this paper, the influence of this redistribution layer on the solder joint reliability is investigated. Also the induced stresses in this redistribution layer may not exceed the ultimate stress level. Three different redistribution processes are considered. Finite element simulations and Coffin-Manson based reliability models are used to compare the thermal cycling reliability of redistributed and standard flip chip assemblies. The existence of a photosensitive BCB redistribution layer on the chip influences the thermal fatigue of solder joints. The largest reliability improvement using redistributed chips is achieved by moving the solder joints from the perimeter to the interior of the die resulting in an area array flip chip.

Antenna arrays in MCM-D technology fed by coplanar CPW networks

Abstract: In this paper, the design, fabrication, and characterization of planar antenna arrays in the MCM-D technology are presented. The arrays are fed by coplanar feeding networks built using coplanar-waveguide lines. 2/spl times/2 and 4/spl times/4 arrays of slot dipoles designed to work in K-band, around 25 GHz, are also presented. The analysis was carried out both theoretically and experimentally. The results include the return loss, radiation patterns, and antenna gain. The proposed arrays are compatible with the driving electronics technology, enjoying high-impedance bandwidth, low cross polarization, high gain, and high radiation efficiency.

Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques

Abstract: The bond pad design on a chip can be reconfigured to a new pad design using a redistribution layer, based on multichip module-deposited (MCM-D) technology. The new pad configuration can be used for flip chip mounting. The thermo-mechanical reliability of these redistributed flip chip structures is in particular determined by the viseo-plastic deformations of the solder joints and by the stresses in the photosensitive BCB redistribution layers. In this paper, the influence of this redistribution layer on the solder joint reliability will be investigated. Also the induced stresses in this redistribution layer may not exceed the ultimate stress level. Three different redistribution processes are considered. Finite element simulations and Coffin-Manson based reliability models are used to compare the thermal cycling reliability of redistributed and standard flip chip assemblies. The existence of a photosensitive BCB redistribution layer on the chip influences the thermal fatigue of solder joints. The largest reliability improvement using redistributed chips is achieved by moving the solder joints from the perimeter to the interior of the die resulting in an area array flip chip.

Advances in microwave MCM-D technology

Abstract: The thin film multilayer multichip module technology (MCM‐D) was originally used for the interconnection of high speed digital circuits in a single module. Nowadays, the technology is more and more evolving towards use in the interconnection of RF and microwave circuits with integrated passive components. This paper gives an overview of this evolution towards microwave MCM‐D technology and the recent advances with respect to the integration of high quality passive components. With a discussion on the flip chip mounting of active devices, the link towards fully integrated high frequency front‐end systems is pointed out.

Chip-package co-design of a 4.7 GHz VCO

Abstract: Wireless communication applications require low-power and highly integrated transceiver solutions. In particular, the integration of the RF front-end poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. "Single-package" integration of complete transceivers based on an MCM-D technology with integrated passives is presented in this paper as a superior alternative to overcome the many problems of single-chip CMOS integration. To benefit from all the advantages offered by this approach, a careful co-design of ICs and package is required. This is illustrated with the design of a 4.7 GHz VCO for a 5.2 GHz HIPERLAN-2 application.

Integrated passives for a DECT VCO

Abstract: Today's wireless radio applications such as DECT, require highly integrated transceiver solutions. However, traditional front-end implementations require a large number of discrete components. As most of these components are passive devices and as the active devices are integrated on only a few chips, cost effective integration of the passive devices into the interconnection substrate is a very attractive approach. This work presents the use of thin film MCM-D technology for the integration of a VCO circuit. The circuit itself contains a resonator, a negative resistance, an isolation amplifier stage and a transmit/receive switch. In our approach 4 active devices (2 bare die diodes and 2 bare die bipolar transistors) have to be placed on the module, while 28 other passives are fabricated on the glass substrate. The integrated MCM-D passives used in the circuit are TaN resistors, high Q spiral inductors, BCB- and Ta 2 O 5 -capacitors At 925 MHz the VCO shows an output power of-5 dBm and a phase noise performance of-109.7 dBc/Hz at 100 kHz off the carrier as predicted from simulations. A thorough characterisation will be presented. This thin film MCM-D approach also allows a size reduction with a factor of five as compared to a discrete realisation of the same function.

MCM-D technology for integrated passives components

Abstract: Integrated passive components are becoming of growing importance for new telecommunication circuits In this paper, a thin film multilayer MCM-D technology for the integration of almost any type of passive structure is presented The capabilities of the technology are demonstrated up to microwave frequencies through the examples of various realized integrated passive components

Method for fabricating a thin film build-up structure on a sequentially laminated printed circuit board base

Abstract: Method and apparatus of fabricating a core laminate Printed Circuit Board structure with highly planar external surfaces is provided. A pre-formed flat material including a first resinous sub-material and a second carrier sub-material is used to planarize external surfaces. During lamination, uniform pressure is applied to the pre-formed flat sheet which covers the upper surface of the printed circuit. The resinous material of the first sub-material flows to fill the crevices, vias, etc. of the upper surface of the PCB. Moreover, due to the uniform pressure on the pre-formed flat sheet, the resinous first sub-material is planarized. This planarized surface provides a suitable base substrate for a thin film multilayer build-up structure and that provides electrical connections between the thin film top layers and the Printed Circuit Board—style core layers.

Sequential-rotation arrays of circularly polarized CPW-fed aperture antennas in the MCM-D technology

Abstract: This paper describes the design and characterization of a 2/spl times/2 sequential-rotation array (SRA) of novel circularly polarized antenna elements The required feed phase-vector is achieved using a coplanar feeding network The network is, for the first time, built using CPW lines in MCM-D technology The array operates in the K-band around 25 GHz The analysis is carried out both theoretically and experimentally The results show that the sequential rotation increases the axial ratio bandwidth and enhances the isolation between the RHCP and LHCP polarizations The proposed antenna element and sequential-rotation array enjoy high impedance bandwidth, high circular polarization bandwidth, and good isolation between the RHCP and the LHCP modes

Chip-package co-design of a 4.7 GHz VCO

Abstract: Future wireless communication applications require low-power and highly integrated transceiver solutions Especially the integration of the RF front-end poses a great challenge, as traditional implementations require a large number of external passive components. Single-package integration of complete transceivers based on an MCM-D technology with integrated passives is presented in this paper as a superior alternative to overcome the many problems of single-chip CMOS integration. Unloaded Q's of on-chip inductors are typically not higher than 5, which limits e.g. the phase noise performance of a VCO circuit. In our MCM-D technology inductors with Qs higher than 50 are easily integrated. Active RF components can be assembled to the MCM substrate using flip-chip technology. The parasitics introduced in this way are much lower as compared to traditional chip bonding and packaging. To benefit from all the advantages offered by this approach a careful co-design of ICs and passive components on the package is necessary. As an illustration, a 4.7 GHz VCO for a 5.2 GHz HIPERLAN-2 application is designed. The VCO consists of a core integrated in 0.35 μm BiCMOS technology and accompanying inductors for the resonator, which are integrated in the thin film MCM-D technology. This single-package solution results in a 5 dB phase noise reduction and at the same time the power consumption is lowered by almost a factor of 2 (18 mW to 9.5 mW) as compared to a single-chip design.

Image sensor.ball grid array.package and manufacture thereof

Abstract: PROBLEM TO BE SOLVED: To eliminate generation of a Newton ring between a transparent cover and a die, by partitioning with a wall including a metal seal the substrate including optical sensitive area and the transparent substrate, and then surrounding the substrate circuit including the optical sensitive area with the wall. SOLUTION: An image sensor.ball grid array includes the sealed cavity, and the cavity is specified with a wall 13 depending on the geometrical shape closed between a first substrate 12 and a second substrate 13 (transparent substrate). The wall 13 is a laminated material at least consisting of a first metal covered layer, a reflow solder layer and a second metal covered layer, surrounding at least one optical area formed on the first substrate 12. The image sensor.ball grid array may also be provided with the desired third substrate 16 (for example, BGA substrate). As a result, humidity and diffusion of epoxy can be prevented between the image sensor and transparent cover. Moreover, generation of Newton ring can also be eliminated between the transparent cover and die.

New ultrathin 3D integration technique: technological and thermal investigations

Abstract: A new vertical chip integration is proposed, based on the UTCS concept. It consists in stacking thinned chips on top of a silicon substrate. Lateral and vertical metal interconnections and the thinned chips are embedded in BCB layers. This wafer scale integration technique is presented. Thermal behavior of such stacked structure is also discussed.

Realisation of a DECT VCO circuit with MCM-D technology

Abstract: Wireless radio applications such as DECT require highly integrated transceiver solutions. In particular, the integration of the RF front-end poses a great challenge in these applications, as traditional front-end implementations require a large number of components. As most of these components are passive devices and as the active devices are integrated on only a few chips, cost effective integration of those devices into the interconnection substrate is a very attractive approach. This paper presents the use of thin film MCM-D technology for the integration of a VCO circuit. The circuit itself contains a resonator, a negative resistance and an isolation amplifier stage, which are all integrated on the MCM glass substrate. In this approach, only 4 active devices (2 diodes and 2 bipolar transistors) have to be placed on the module; the 28 other passives (including inductors, capacitors and resistors) are fabricated within the glass substrate, using multilayer thin film techniques. The use of integrated passives also allows size reduction by a factor of five as compared to discrete realization of the same function.

Galerkin versus razor-blade testing in the method of moments formulation for multiconductor transmission lines

Abstract: In this paper, the effect of the testing technique in the method of moments (MoM) solution for multiconductor transmission lines is investigated. Two important testing techniques, namely, Galerkin and razor-blade testing, are used and compared. The problem is formulated using the mixed potential integral equation. The analysis shows that the solution of the longitudinal modal current near the edge of the conductor is significantly affected by the testing scheme in the MoM kernel. For the selected expansion functions, razor-blade testing gives more reasonable modal current distribution than Galerkin testing. © 2000 John Wiley & Sons, Inc. Int J RF and Microwave CAE 10: 132–138, 2000.

A Quantitative Study of the Adhesion Between Copper, Barrier and Organic Low-K Materials

Abstract: The adhesion between several materials implemented in Cu/low-k integration is studied. Adhesion issues at different interfaces are important with regard to the reliability of back-end processing. Layered test structures are processed to study different interfaces. A tangential shear tester allows quantifying the adhesion force at the interface and provides a relative measurement to compare various materials. Failed interfaces are analyzed using auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Among all studied structures, the strongest interface is seen between a barrier (Ti(N), Ta(N), W x N) and Cu. A weaker interface proves to be between a low-k dielectric and Cu. However, the presence of a barrier increases the adhesion. The weakest interface occurs between an oxide cap and the low-k material, with a lower adhesion when the low-k material is fluorinated. The low-k/cap oxide interface forms a critical issue with regard to Cu/low-k integration processing such as chemical mechanical polishing (CMP). All test structures show no significant degradation of the adhesion after a thermal cycle up to 400°C.

Packaging for MEMS and MST devices : The indent reflow sealing method

Abstract: A variety of micro electo-mechanical system, MEMS, or microsystem, MST devices requires encapsulation of their crucial parts in a hermetically sealed cavity for reasons of protection, reliability and tuning of performance. Chances for damaging the fragile movable parts are minimized if the cavity is realized at a very early packaging stage, conveniently referred to as the 0-level or wafer-level packaging. In this article, a novel 0-level packaging method, called the indent-reflow-sealing (IRS) technique, will briefly be described. Application of the IRS method to the fabrication of a MEMS relay will be illustrated. More details on the IRS method can be found in ref. [1] ].

Trends in packaging and high density interconnection

Abstract: In this paper, some of the main trends in packaging and interconnection technology for microelectronic devices are reviewed Particular attention is given to the impact of the evolution of microelectronic technology on the requirements for electronic packaging

Residual thermomechanical stresses in ultrathin chip stack technology

Abstract: The aim of this work is to analyze the thermo-mechanical stresses evolution produced during the fabrication sequence of themulti-level UTCS structure. Several non-linear material models have been taken into account during the process modeling.We have therefore resorted to the Finite Element Method for the evaluation of such thermo-mechanical stresses that appearsin the manufacturing and stacking process. These efforts are made to optimize the product and process design.Keywords: residual stress, FEM, chip stack, creep, BCB, copper, interconnects, MCM 1. INTRODUCTION UTCS will deliver a new, very dense, 3D stacking technology for semi-conductor chips. This very dense, ultra thin stackingtechnology is of interest to all electronics industries where size and weight are important for product acceptance. Anotheradvantage for industry is the possibility of using standard chips form different vendors. The proposed new, dense stack willbe based on photosensitive Benzocyclobutene (onwards BCB). The procedure is as follows: the chips are thinned down to1 0-15 im and then, using planarisation techniques as used in semiconductor processing, the 3D stack is formed on a siliconsubstrate by depositing layers of dielectric, onto which a metallisation copper structure is patterned. The thinned chips areplaced on top of each dielectric layer and the vertical interconnection is realised with metal vias.This technology has required the development of a thinning technology applicable to standard fmished silicon chips thatachieve a fmal thickness in the order of 10-15 tm using chemical and mechanical procedures. Another challenging pointthat required some improvements was the development of transport, attachment and bonding solutions for the very thinsilicon chips that are used in the 3D stack. Also the existing planarisation techniques used in this stacking methodology hadto be duly modified.During the sequential built-up of the UTCS structure the constituent materials suffer thermal cycling, see 1 for a detailedthermal and technological description. The differences in the coefficients of thermal expansion (CTE) between dissimilarmaterials inevitably generate thermal residual stresses. These stresses may exceed the strength of the films resulting incracking, the interface may fail resulting in delamination or the excessive warping may hinder further processing. Is the aimof this work the evaluation of this potential source of problems for the UTCS technology by making use of the fmiteelement method2. Despite many works3'4'5 have been devoted to the analytical study of thermal stresses in multilayeredassemblies, the mathematical intricacies which easily arise, do only allow very simple geometries, and in consequence areoflittle applicability in a complex structure such as the UTCS.To be able to study these residual stresses we use a parametric process-modelling framework to simulate the evolution ofstresses and strains as the structure is sequentially fabricated6'7. This is in contrast to the usual approach of many researcherswho employ a "frozen-view" model starting from the geometry of the fmal configuration. In the "frozen-view" model, theentire structure is assumed to be stress-free at the curing temperature of the polymer and then cooled down to the roomtemperature. This procedure provides a better understanding of the process because the material layers are deposited atdifferent temperatures, and therefore, not all layers are stress-free at the same temperature. Furthermore, residual stressesmay develop plastic deformations at intermediate process steps, a feature that can not be captured by "frozen models".

High-Q Inductors for Realization of Low Insertion Loss Baluns and Couplers Integrated in Thin Film Multilayer MCM-D Technology for Wireless Applications

Abstract: This paper presents spiral inductors with quality factors of more than 100 in a thin film muli-layer MCM-D technology. Together with other passive components, such as capacitors, resistors or interconnection lines, these spiral inductors are used to realize integrated baluns and various types of couplers for front-end systems for wireless application. Because o f the high-Q of the inductors and the high overall performance of the integrated passive components in general, the insertion loss of the baluns and couplers is kept very low. This, together with the enhanced miniaturization, leads to higher packaging densities and lower cost of wireless applications.

Analysis and design of two types of microwave baluns

Abstract: Theoretical analysis and experimental realization of two types of microwave baluns is presented. Both baluns are made from coupled strip lines with one input and two output ports. The power outputs from the output ports are equal and anti-phased over a certain bandwidth. Conditions for perfect balance, at least at the center frequency, are stated and parametric sensitivity analysis is given analytically.