Showing papers by "Heng-Yuan Lee published in 2017"

A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

Abstract: Recent ReRAM devices enable the development of computing-in-memory (CIM) for beyond von Neumann structure However, wide distribution in ReRAM resistance (R) causes low yield for CIM operations This work proposes a dual-mode computing (DMc) ReRAM macro structure with a dual-function voltage-mode self-write termination (DV-SWT) scheme to achieve both memory and fundamental CIM functions (AND, OR and XOR operations) with high yield The DV-SWT increases the read margin for CIM operations by suppressing the R-variations caused by macro-level IR-drop and process variations A 16Mb DMc-ReRAM full-function macro was fabricated using 1T1R HfO ReRAM devices and 015um CMOS process The measured delay of the CIM operations is less than 14ns, which is 86+x faster than previous ReRAM-based CIM works This work also represents the first CIM ReRAM macro with ReRAM device and CIM-peripheral circuits fully integrated on the same die

The Role of Ti Buffer Layer Thickness on the Resistive Switching Properties of Hafnium Oxide-Based Resistive Switching Memories

Abstract: Ti/HfOx-based resistive random access memory (RRAM) has been extensively investigated as an emerging nonvolatile memory (NVM) candidate due to its excellent memory performance and CMOS process compatibility. Although the importance of the role of the Ti buffer layer is well recognized, detailed understanding about the nature of Ti thickness-dependent asymmetric switching is still missing. To realize this, the present work addresses the effects of Ti buffer layer thickness on the switching properties of TiN/Ti/HfOx/TiN 1T1R RRAM. Consequently, we have demonstrated a simple strategy to regulate the FORMING voltage, leakage current, memory window, and decrease the operation current, etc. by varying the thickness of the Ti layer on the HfOx dielectrics. Accordingly, controllable and reliable bipolar, complementary, and reverse bipolar resistive switching (BRS, CRS, and R-BRS) properties have been demonstrated. This work also provides the direction to avoid unwanted CRS properties during the first RESET operat...

Scalability and reliability issues of Ti/HfOx-based 1T1R bipolar RRAM: Occurrence, mitigation, and solution

Abstract: Scalability and reliability issues are the most dominant obstacle for the development of resistive switching memory (RRAM) technology Owing to the excellent memory performance and process compatibility with current CMOS technology of Ti/HfOx-based filamentary type bipolar RRAM, its scalability and reliability issues have been investigated in this document Towards this goal, we demonstrate that there exists a clear correlation between the transistor and memory cell, which ultimately limits the scaling in terms of operation current and size of the transistor as well and performance of the Ti/HfOx-based 1T1R bipolar RRAM Due to the resemblance of switching behaviour between complementary resistive switching, ie, CRS in a single memory stack, and bipolar resistive switching, the Ti/HfOx-based bipolar RRAM suffers from resistance pinning (RP) issues, whereas the minimum resistance during the 1st RESET operation always impeded below 20 kΩ; this occurs through the interaction between the transistor and memo

Retention Model of TaO/HfO x and TaO/AlO x RRAM with Self-Rectifying Switch Characteristics

Abstract: A retention behavior model for self-rectifying TaO/HfO x - and TaO/AlO x -based resistive random-access memory (RRAM) is proposed. Trapping-type RRAM can have a high resistance state (HRS) and a low resistance state (LRS); the degradation in a LRS is usually more severe than that in a HRS, because the LRS during the SET process is limited by the internal resistor layer. However, if TaO/AlO x elements are stacked in layers, the LRS retention can be improved. The LRS retention time estimated by extrapolation method is more than 5 years at room temperature. Both TaO/HfO x - and TaO/AlO x -based RRAM structures have the same capping layer of TaO, and the activation energy levels of both types of structures are 0.38 eV. Moreover, the additional AlO x switching layer of a TaO/AlO x structure creates a higher O diffusion barrier that can substantially enhance retention, and the TaO/AlO x structure also shows a quite stable LRS under biased conditions.

Analyzing inference robustness of RRAM synaptic array in low-precision neural network

Abstract: In this work, we investigate the robustness of 1-transistor-1-resistor (1T1R) synaptic array to implement a low-precision neural network. The experimental results on 1 kb HfO x -based RRAM array show a large on/off ratio (i.e. > 105×) and 5 stable resistance states can be reliably achieved with 10× window between adjacent two states. As the RRAM has the resistance drift over time under read voltage stress, the impact of read disturbance occurred in 1T1R synaptic array on the neural network classification accuracy is analyzed with the RRAM compact model fitted with experimental data. The simulation results of a single-layer perceptron with compressed MNIST dataset indicate that 1) more stable multi-level states are desired to have higher mapping capability of weights, thus achieving a higher initial classification accuracy; 2) good mapping strategies that avoid the read disturbance-induced sign change on the most significant weight levels are very important to mitigate the classification accuracy loss.

Occurrence and solution to overcome 1 st RESET resistance pinning effect in Ti/HfO x based RRAM for low power nonvolatile memory applications

Abstract: In summary, we have optimized the operation current to obtain stable endurance and retention properties in Ti/HfO x based bipolar RRAM for future low power nonvolatile memory applications. Furthermore, the 1st RESET resistance pinning effect after the FORMING process at lower current is greatly improved by selecting the Ti/HfO x thickness ratio in TiN/Ti/HfO x /TiN 1T1R RRAM. Thus, in order to achieve the reliable switching at low operation current, the design of the memory element is crucial.