https://www.thelancet.com/pdfs/journals/lancet/PIIS0140-6736(06)68880-6.pdf

Mild cognitive impairment

This article attempts to bring together basic and complex information which has been gathered on cellulose structure, principally that of native cellulose, over the last few decades. Even though advances have been made in the field of crystallography, powder crystallography cannot yield a definitive cellulose structure and single crystal diffraction is not possible due to the lack of suitable crystals. Knowledge obtained on the biosynthesis of native cellulose and on the polymorphy of cellulose and its derivatives help our understanding of ultrastructure. Many inconsistencies between early crystallographic studies of native cellulose have been clarified by the discovery that two polymorphs (α and β) of cellulose I exist. Models of the possible ultrastructural arrangements within native cellulose have been put forward over the decades; with advancement in technology, computer simulations of small and large systems are being created to test the viability of these ultrastructural models. It is hoped that this review will aid in the understanding of the complexity and uncertainties that still exist in this subject

Cellulose: the structure slowly unravels

Summary Early diagnosis of Alzheimer's disease (AD) is needed to initiate symptomatic treatment with acetylcholinesterase inhibitors, and will be of even greater significance if drugs aimed at slowing down the degenerative process, such as vaccination regimes and β-secretase and γ-secretase inhibitors, prove to affect AD pathology and to have clinical effect. However, there is no clinical method to determine in which patients mild cognitive impairment (MCI) will progress to AD with dementia, and in which patients MCI is benign. Hence, there is a great clinical need for biomarkers to identify incipient AD in patients with MCI. The CSF biomarkers total tau protein, phosphorylated tau protein, and the 42 amino-acid residue form of amyloid-β may, if put in the right clinical context, prove to have high enough diagnostic accuracy to meet this challenge.

https://www.thelancet.com/pdfs/journals/laneur/PIIS1474-4422(03)00530-1.pdf

CSF markers for incipient Alzheimer's disease

Chromatographic separation, identification, and analysis of phosphatides

Activation by Adenosine Triphosphate in the Phosphorylation Kinetics of Sodium and Potassium Ion Transport Adenosine Triphosphatase

Broadband and Flexible Receiver Architecture for Software Defined Radio Terminal Using Direct Conversion and Low-IF Principle

A fully integrated 4 $\times $ 4 802.11abgn/ac/ax transceiver system-on-chip (SoC) with integrated interference analyzer and frequency-dependent in-phase and quadrature (IQ) (FD-IQ) calibration is presented. The FD-IQ technique helps meeting the extremely strict IQ imbalance requirement for 1-K quadratic-amplitude modulation (QAM). The pure current-mode TX baseband (BB) improves SNR to better than 50 dB, and a multi-mode local oscillator (LO) distribution circuit provides non-contiguous operation with the error vector magnitude (EVM) of less than −37 dB. The integrated interference analyzer achieves the highly reliable connection in the presence of the undesired signal and hence improves the frequency usage efficiency by identifying the wireless LAN (WLAN) and other signals in the 2G/5G band.

An 802.11ax 4 $\times$ 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer

When the input signal IN1 changes from a ground voltage GND to a first voltage -E1 and from the first voltage -E1 to the ground voltage GND, the output potential of the -E2 system flip-flop circuit changes gradually. The inverted signal from the -E1 system inverter circuit is supplied to the -E2 system inverter circuit earlier than the output signal (high-potential signal) of the -E2 system flip-flop circuit. This eliminates a period of time when all the MOSFETs in the -E2 system inverter circuit turn on simultaneously, thereby reducing a through current in the -E2 system inverter circuit. Consequently, the circuit operation can be stabilized by decreasing through currents flowing in the -E1 system inverter circuit and the -E2 system inverter circuit using the output signal of the -E2 system flip-flop circuit as an input.

Level shifting low to high supply voltage interface circuit

PROBLEM TO BE SOLVED: To overcome the deterioration of a reception characteristic caused by a DC offset generated when a received signal is processed in an analog signal processing circuit and to realize a satisfactory call. SOLUTION: An analog signal processing circuit 2 processing an analog signal inputted from a signal input part 1 and generating the unnecessary DC offset in a signal route and a digital signal processing circuit 4 which A/D- converts 3 the output and processes a converted digital signal are provided for a receiver. The digital signal processing circuit is provided with offset detection means 401 and 402 for detecting the offset and means 403 and 404 for holding the detected DC offset. A D/A converter converts a part of the DC offset which is held into an analog signal, and a second DC offset correction means provided for the analog signal processing circuit reduces the DC offset and removes the DC offset generated in the analog signal processing circuit.

Receiver provided with dc offset removal function and radio communication system using the same

In direct conversion receivers, which down-convert RF signal to baseband directly, DC offset in the baseband signal significantly degrades receiver performance and thus the DC offset cancellation is one of the most important issues regarding the achievement of high receiving performance. This paper proposes a fast-settling DC offset canceller that eliminates DC offset using stored DC data estimated in advance so as to cancel residual DC offset by a feedback loop. Experimental results and computer simulation results show that the DC offset canceller can eliminate a DC offset within 5 [musec], although it does not remove the desired signal component so as not to degrade BER (bit error rate) performance, because cut-off frequency in the HPF (high-pass filter) characteristic due to DC offset cancellation can remain low.

Hiroshi Yoshida

Papers

Broadband and Flexible Receiver Architecture for Software Defined Radio Terminal Using Direct Conversion and Low-IF Principle

An 802.11ax 4 $\times$ 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer

Level shifting low to high supply voltage interface circuit

Receiver provided with dc offset removal function and radio communication system using the same

A Direct Conversion Receiver with Fast-Settling DC Offset Canceller