Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The goal of this paper is to review in brief the basic physics of single-election devices, as well as their-current and prospective applications. These devices based on the controllable transfer of single electrons between small conducting "islands", have already enabled several important scientific experiments. Several other applications of analog single-election devices in unique scientific instrumentation and metrology seem quite feasible. On the other hand, the prospect of silicon transistors being replaced by single-electron devices in integrated digital circuits faces tough challenges and remains uncertain. Nevertheless, even if this replacement does not happen, single electronics will continue to play an important role by shedding light on the fundamental size limitations of new electronic devices. Moreover, recent research in this field has generated some by-product ideas which may revolutionize random-access-memory and digital-data-storage technologies.

Single-electron devices and their applications

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

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Device scaling limits of Si MOSFETs and their application dependencies

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.

Forming steep lateral doping distribution at source/drain junctions

A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.

Logic circuits having linear and cellular gate transistors

A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Patterned buried insulator

The present invention relates to a recessed channel/gate MOSFET structure which comprises a semiconductor wafer having a plurality of shallow trench isolation regions embedded therein, wherein between each adjacent shallow trench isolation region is a field effect transistor region which comprises a source and drain region which are spaced apart by a gate region, said gate region comprising a poly gate region which is positioned between oxide spacers, said poly gate region having a metal contact region on its top surface and a gate oxide region on its bottom surface embedded in said semiconductor wafer and wherein said source and drain regions have an extension which wraps around said oxide spacers and provides a connection with a channel region which is formed below said gate oxide region.

Hsing-Jen Wann

Papers

CMOS scaling into the nanometer regime

Forming steep lateral doping distribution at source/drain junctions

Logic circuits having linear and cellular gate transistors

Patterned buried insulator

Recessed-gate MOSFET with out-diffused source/drain extension