Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or 'high K' gate oxides such as hafnium oxide and hafnium silicate. Little was known about such oxides, and it was soon found that in many respects they have inferior electronic properties to SiO2 ,s uch as a tendency to crystallise and a high concentration of electronic defects. Intensive research is underway to develop these oxides into new high quality electronic materials. This review covers the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects. The use of high K oxides in capacitors of dynamic random access memories is also covered.

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High dielectric constant oxides

The goal of this paper is to review in brief the basic physics of single-election devices, as well as their-current and prospective applications. These devices based on the controllable transfer of single electrons between small conducting "islands", have already enabled several important scientific experiments. Several other applications of analog single-election devices in unique scientific instrumentation and metrology seem quite feasible. On the other hand, the prospect of silicon transistors being replaced by single-electron devices in integrated digital circuits faces tough challenges and remains uncertain. Nevertheless, even if this replacement does not happen, single electronics will continue to play an important role by shedding light on the fundamental size limitations of new electronic devices. Moreover, recent research in this field has generated some by-product ideas which may revolutionize random-access-memory and digital-data-storage technologies.

Single-electron devices and their applications

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

CMOS scaling into the nanometer regime

Quantum-mechanical modeling of electron tunneling current from the quantized inversion layer of ultra-thin-oxide (<40 /spl Aring/) nMOSFET's is presented, together with experimental verification. An accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitance-versus-voltage curves to quantum-mechanically simulated capacitance-versus-voltage results. The lifetimes of quasibound states and the direct tunneling current are calculated using a transverse-resonant method. These results are used to project an oxide scaling limit of 20 /spl Aring/ before the chip standby power becomes excessive due to tunneling currents,.

Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

The electrical characteristics (C-V and I-V) of n+ - and p+ -polysilicon-gated ultrathinoxide capacitors and FETs were studied extensively to determine oxide thickness and to evaluate tunneling current. A quantum-mechanical model was developed to help understand finite inversion layer width, threshold voltage shift, and polysilicon gate depletion effects. It allows a consistent determination of the physical oxide thickness based on an excellent agreement between the measured and modeled C-V curves. With a chip standby power of ≤0.1 W per chip, direct tunneling current can be tolerated down to an oxide thickness of 15-20 A. However, transconductance reduction due to polysilicon depletion and finite inversion layer width effects becomes more severe for thinner oxides. The quantum-mechanical model predicts higher threshold voltage than the classical model, and the difference increases with the electric field strength at the silicon/oxide interface.

Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides

Junctionless double-gate (DG) MOSFETs are assessed by analyzing the on-off characteristics of the mobile charge density as a function of gate voltage. Compared with undoped DG MOSFETs, junctionless MOSFETs have an inferior on-off charge performance with more degradation at higher doping. The results also indicate a major issue: dopant number fluctuations in minimum width junctionless MOSFETs. A first-order analytic expression shows that the one-sigma threshold fluctuation is proportional to the square root of doping concentration. Inclusion of the quantum effect makes no significant difference to the results.

Shih-Hsien Lo

Papers

CMOS scaling into the nanometer regime

Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's

Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides

On–Off Charge–Voltage Characteristics and Dopant Number Fluctuation Effects in Junctionless Double-Gate MOSFETs