Hwan Sung Choe

TL;DR: An architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm2, representing a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

TL;DR: Simulations show that the bandwidth of this branched intracellular nanotube FET (BIT-FET) is high enough for it to record fast action potentials even when the nanot tube diameter is decreased to 3 nm, a length scale which is well below that accessible with other methods.

TL;DR: Large anisotropy in in-plane thermal conductivity of single-crystal black phosphorus nanoribbons along the zigzag and armchair lattice directions at variable temperatures is reported.

TL;DR: In this article, a rare chemical form of arsenic, called black-arsenic (b-As), is reported as a cousin of black phosphorus, as an extremely anisotropic layered semiconductor.

TL;DR: Ferroelectrically driven nonvolatile memory is demonstrated by interfacing 2D semiconductors and ferro electric thin films, exhibiting superior memory performance comparable to existing thin-film ferroelectric field-effect transistors.