How to control solid state dewetting: A short review

Strain in Si nanostructures is used to achieve higher carrier mobility, making these devices candidates for the next generation of transistors. Minamisawa et al. fabricate silicon nanowires subject to elastic tensile strain up to 4.5%, exceeding the limit achievable with the use of SiGe virtual substrates.

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Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the Smart CutTM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a “semiconductor on insulator” structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator (“SGOI”) substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented.

Engineering strained silicon on insulator wafers with the Smart CutTM technology

We have studied the etching of silicon, SiGe and germanium layers with gaseous HCl in reduced pressure-chemical vapour deposition (RP-CVD). We have observed the occurrence of two etch regimes depending on the etching temperature. The first regime takes place at high temperatures and is characterized by low activation energies (~7 kcal mol−1), this whatever the germanium content of the etched layer. The other regime occurs at low temperatures and has associated high activation energies (which strongly depend upon the germanium concentration of the etched layer: 86 kcal mol−1 for pure Si versus 28 kcal mol−1 for pure Ge). Modifying the HCl partial pressure has different effects depending on the regime. In the high temperature regime, increasing the HCl partial pressure will almost quadratically increase the etch rate (ER ∝ PHCl1.76), this both for Si and Si0.67Ge0.33. Meanwhile, the dependence is sub-linear in the low temperature regime (Si ER ∝ PHCl0.53 and Si0.67Ge0.33 ER ∝ PHCl0.82). The temperature where the regime shifts from one to the other decreases when the Ge concentration increases. To illustrate the added value of the chemical vapour etching, we have demonstrated two possible applications. The first one is the realization of SiGe thin strain relaxed buffers (TSRBs) in the active areas of shallow trench isolation (STI) patterned wafers after etching away the silicon with HCl. We have observed the occurrence of some etching loading effects when moving from a blanket to a patterned wafer. The SiGe TSRBs exhibit some good structural properties (rms roughness of 0.12 nm, no defects observed in cross-sectional transmission electron microscopy). However, they are not fully relaxed and facets are present at the STI/epitaxial stack boundary, signifying they are still not mature enough to be integrated in a metal oxide semiconductor technology. Another possible application is to decorate through some in situ HCl etching the dislocations threading through SiGe relaxed thick layers, with some significant advantages over commonly used wet etching solutions such as the Secco and the Schimmel ones.

https://iopscience.iop.org/article/10.1088/0268-1242/20/2/004/pdf

Chemical vapour etching of Si, SiGe and Ge with HCl; applications to the formation of thin relaxed SiGe buffers and to the revelation of threading dislocations

Applying stress to induce appropriate strain in the channel region of metal-oxide-semiconductor field effect transistors (MOSFETs) increases both electron and hole mobilities in the strained channel as stated in R People (1986), J J Welser et al (1994), C K Maiti et al (1998) and D J Paul (2004) Furthermore, interest is driven by the possibility of creating electronic devices as well as integrating existing devices in different materials systems, leading to the production of integrated circuits with increased functionality and lower cost In this article, we review various mobility enhancement techniques, such as substrate-enhancement, including stain, Ge/SiGe channels, orientations, process-induced strain, and package-strain (external mechanical strain)

Mobility-enhancement technologies

Strained Silicon On Insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, this new technology potentially combines enhanced devices scalability allowed by thin films and enhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate by experimental results how a layer transfer technique such as the Smart Cut™ technology can be used to obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments and characterizations will be used to characterize these engineered substrates and show that they are compatible with the applications.

Strained Silicon On Insulator wafers made by the Smart Cut™ technology

In microelectronics, photonics, opto-electronics, high frequency or high power device applications, the needs for specific substrate solutions are more and more required. Smart Cut™ technology appears as the technological answer that enables the industrial to provide engineered substrate solutions tailored to the applications. For instance a large spectrum of SOI type structures are today in volume manufacturing. At present the industrial is focused on composite substrates. This paper focuses on the realization of advanced SOI, strained SOI, SOQ substrates and many other examples of engineered substrates. Highlights are given on the most recent developments.

I. Cayrefourq

Papers

Engineering strained silicon on insulator wafers with the Smart CutTM technology

Strained Silicon On Insulator wafers made by the Smart Cut™ technology

Smart Cut Technology: The Path for Advanced SOI Substrates