Iouliia Skliarova

TL;DR: This paper presents methods for optimization of finite state machines for FPGA-based circuits and systems and designs of digital circuits and system on the basis of FPGAs.

TL;DR: In this paper, the state-of-the-art in reconfigurable hardware SAT satisfiers is presented, and the analysis and classification of existing systems has been performed according to such criteria as algorithmic issues, reconfiguration modes, the execution model, the programming model, logic capacity, and performance.

TL;DR: A novel approach for solving the Boolean satisfiability (SAT) problem by combining software and configurable hardware that avoids instance-specific hardware compilation and allows the total problem solving time to be reduced compared to other approaches.

TL;DR: This paper presents the state-of-the-art in reconfigurable hardware SAT satisfiers, which have been performed according to such criteria as algorithmic issues, reconfiguration modes, the execution model, the programming model, logic capacity, and performance.

TL;DR: The paper found that the even-odd transition network is the most regular network that can be implemented very efficiently in FPGA, so it is proposed new, easily scalable hardware solutions and processing techniques based on this.