J. Franco

TL;DR: This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution and analyzes and quantify the benefits observed due to sequential scaling at a die level.

TL;DR: In this article, a gate-first dual Si/SiGe channel low-complexity integration approach was proposed for low V t (V t,Lg=1µm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ∼8A using a gate first dual Si and SiGe channel integration approach.

TL;DR: This work demonstrates the successful integration of 0.85nm-EOT Si-pFETs using a gate first approach, outperforming the state-of-the-art Si-channel reference and significant improvements at lower VDD have been confirmed through complex circuit simulations and validated by experimental results.

TL;DR: In this article, the authors presented and validated an oxide defect model to investigate the improvement in positive bias temperature instabilities due to a reliability anneal and corroborated the simulated defect bands with prior defect-centric studies and perform lifetime projections.

TL;DR: In this article, a broad study of negative bias temperature instability in replacement metal gate (RMG) SiGe core FinFETs is presented, focusing on the impact of Ge concentration, fin width, fin side-wall orientation, and interface passivation by high pressure anneals (HPA).