S
Shinji Takeoka
Researcher at Panasonic
Publications - 20
Citations - 218
Shinji Takeoka is an academic researcher from Panasonic. The author has contributed to research in topics: Transistor & Semiconductor device. The author has an hindex of 9, co-authored 20 publications receiving 215 citations.
Papers
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Proceedings Article
Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS
Anabela Veloso,Lars-Ake Ragnarsson,Moon Ju Cho,Katia Devriendt,Kristof Kellens,Farid Sebaai,Samuel Suhard,Stephan Brus,Y. Crabbe,Tom Schram,E. Rohr,Vasile Paraschiv,Geert Eneman,Thomas Kauerauf,Morin Dehan,Soo-jin Hong,S. Yamaguchi,Shinji Takeoka,Higuchi Yuichi,Hilde Tielens,A. Van Ammel,Paola Favia,Hugo Bender,Alexis Franquet,Thierry Conard,Xiang Li,K.-L. Pey,Herbert Struyf,Paul W. Mertens,Philippe Absil,Naoto Horiguchi,T. Y. Hoffmann +31 more
TL;DR: In this paper, gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7A EOT, ∼2x higher f max performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence.
Journal ArticleDOI
SiGe SEG Growth for Buried Channels p-MOS Devices
Andriy Hikavyy,Roger Loo,Liesbeth Witters,Shinji Takeoka,J. Geypen,Bert Brijs,Clement Merckling,Matty Caymax,Johan Dekoster +8 more
Proceedings ArticleDOI
8Å T inv gate-first dual channel technology achieving low-V t high performance CMOS
Liesbeth Witters,Shinji Takeoka,S. Yamaguchi,Andriy Hikavyy,Denis Shamiryan,Moonju Cho,Thomas Chiarella,L.-A. Ragnarsson,Roger Loo,Christoph Kerner,Y. Crabbe,J. Franco,J. Tseng,Wei-E Wang,E. Rohr,Tom Schram,O. Richard,Hugo Bender,Serge Biesemans,Philippe Absil,T. Y. Hoffmann +20 more
TL;DR: In this article, a gate-first dual Si/SiGe channel low-complexity integration approach was proposed for low V t (V t,Lg=1µm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ∼8A using a gate first dual Si and SiGe channel integration approach.
Proceedings ArticleDOI
High-mobility 0.85nm-EOT Si 0.45 Ge 0.55 -pFETs: Delivering high performance at scaled VDD
Jerome Mitard,Liesbeth Witters,M. Garcia Bardon,Phillip Christie,J. Franco,Abdelkarim Mercha,Paolo Magnone,Massimo Alioto,Felice Crupi,L.-A. Ragnarsson,Andriy Hikavyy,Benjamin Vincent,Thomas Chiarella,Roger Loo,J. Tseng,S. Yamaguchi,Shinji Takeoka,W-E. Wang,Philippe Absil,T. Y. Hoffmann +19 more
TL;DR: This work demonstrates the successful integration of 0.85nm-EOT Si-pFETs using a gate first approach, outperforming the state-of-the-art Si-channel reference and significant improvements at lower VDD have been confirmed through complex circuit simulations and validated by experimental results.
Proceedings ArticleDOI
Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel
Geert Hellings,Liesbeth Witters,Raymond Krom,Jerome Mitard,Andriy Hikavyy,Roger Loo,Andreas Schulze,Geert Eneman,Christoph Kerner,Jacopo Franco,Thomas Chiarella,Shinji Takeoka,J. Tseng,Wei-E Wang,Wilfried Vandervorst,Philippe Absil,Serge Biesemans,Marc Heyns,Kristin De Meyer,Marc Meuris,Thomas Hoffmann +20 more
TL;DR: In this article, a novel bulk-Si based pMOSFET structure was presented featuring a high-mobility SiGe 0.45 channel and raised SiGe0.25 source/drains.