Thomas Chiarella

TL;DR: In this paper, the authors report the first demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV), which is inserted between contact and M1 of their reference 0.13 mum CMOS process on 200 mm wafers.

TL;DR: In this paper, an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations is presented. And the authors demonstrate highperforming FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk Fin-FETs.

TL;DR: In this paper, a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors is proposed, based on which they identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution.

TL;DR: In this paper, the authors studied the channel hot carrier degradation mechanisms in n-FinFET devices and showed that in long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG ~ VD/2).

TL;DR: In this article, the authors discuss self-heating effects in scaled bulk FinFETs from 14nm to 7nm node based on 3D FEM simulations and experimental measurements.