S
S. Yamaguchi
Researcher at Katholieke Universiteit Leuven
Publications - 10
Citations - 114
S. Yamaguchi is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: CMOS & Channel (broadcasting). The author has an hindex of 7, co-authored 10 publications receiving 112 citations.
Papers
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Proceedings ArticleDOI
8Å T inv gate-first dual channel technology achieving low-V t high performance CMOS
Liesbeth Witters,Shinji Takeoka,S. Yamaguchi,Andriy Hikavyy,Denis Shamiryan,Moonju Cho,Thomas Chiarella,L.-A. Ragnarsson,Roger Loo,Christoph Kerner,Y. Crabbe,J. Franco,J. Tseng,Wei-E Wang,E. Rohr,Tom Schram,O. Richard,Hugo Bender,Serge Biesemans,Philippe Absil,T. Y. Hoffmann +20 more
TL;DR: In this article, a gate-first dual Si/SiGe channel low-complexity integration approach was proposed for low V t (V t,Lg=1µm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ∼8A using a gate first dual Si and SiGe channel integration approach.
Proceedings ArticleDOI
High-mobility 0.85nm-EOT Si 0.45 Ge 0.55 -pFETs: Delivering high performance at scaled VDD
Jerome Mitard,Liesbeth Witters,M. Garcia Bardon,Phillip Christie,J. Franco,Abdelkarim Mercha,Paolo Magnone,Massimo Alioto,Felice Crupi,L.-A. Ragnarsson,Andriy Hikavyy,Benjamin Vincent,Thomas Chiarella,Roger Loo,J. Tseng,S. Yamaguchi,Shinji Takeoka,W-E. Wang,Philippe Absil,T. Y. Hoffmann +19 more
TL;DR: This work demonstrates the successful integration of 0.85nm-EOT Si-pFETs using a gate first approach, outperforming the state-of-the-art Si-channel reference and significant improvements at lower VDD have been confirmed through complex circuit simulations and validated by experimental results.
Proceedings ArticleDOI
Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration
Liesbeth Witters,Jerome Mitard,Anabela Veloso,Andriy Hikavyy,Jacopo Franco,Thomas Kauerauf,Moonju Cho,Tom Schram,F. Sebai,S. Yamaguchi,S. Takeoka,M. Fukuda,Wei-E Wang,Blandine Duriez,Geert Eneman,Roger Loo,Kristof Kellens,Hilde Tielens,Paola Favia,E. Rohr,Geert Hellings,Hugo Bender,Philippe Roussel,Y. Crabbe,Stephan Brus,G. Mannaert,Stefan Kubicek,Katia Devriendt,K. De Meyer,Lars-Ake Ragnarsson,An Steegen,Naoto Horiguchi +31 more
TL;DR: In this paper, a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration is presented.
Proceedings ArticleDOI
High-mobility Si 1−x Ge x -channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths
Geert Eneman,S. Yamaguchi,C. Ortolland,Shinji Takeoka,Liesbeth Witters,T. Chiarella,Paola Favia,Andriy Hikavyy,Jerome Mitard,Masaharu Kobayashi,R. Krom,Hugo Bender,J. Tseng,Wei-E Wang,W. Vandervorst,Roger Loo,Philippe Absil,Serge Biesemans,T. Y. Hoffmann +18 more
TL;DR: In this paper, the layout dependence of scaled Si 1−x Ge x -channel pFETs is studied and a comprehensive study on the layout dependences of scaled PFET is presented.
Journal ArticleDOI
Layout Scaling of $\hbox{Si}_{1-x}\hbox{Ge}_{x} \hbox{-Channel}$ pFETs
Geert Eneman,S. Yamaguchi,C. Ortolland,S. Takeoka,Masaharu Kobayashi,Liesbeth Witters,Andriy Hikavyy,Jerome Mitard,Roger Loo,T. Y. Hoffmann +9 more
TL;DR: In this article, the effect of elastic stress relaxation on the layout dependence of Si1-xGex-channel p-channel field effect transistors (pFETs) is studied.