Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.

Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

A simple model that links MOSFET performance, in the form of intrinsic switch delay, to effective carrier velocity in the channel is developed and fitted to historical data. It is shown that nearly continuous carrier velocity increase, most recently via the introduction of process-induced strain, has been responsible for the device performance increase commensurately with dimensional scaling. The paper further examines channel material innovations that will be required in order to maintain continued commensurate scaling beyond what can be achieved with process-induced strain, and discusses some of the technological tradeoffs that will have to be faced for their introduction.

Continuous MOSFET performance increase with device scaling: the role of strain and channel material innovations

A new approach is presented aimed at modeling mechanical stress effects which impact MOSFET electrical behavior. It is successful in accounting for mobility variations experimentally evidenced on complex MOSFET geometries. The newly developed mobility model proves to be an efficient way to include mechanical stress effects into standard simulation models. We show that stress effects can and should be taken into account in the IC design phase in present and sub 90 nm nodes CMOS generations.

Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical Performance

The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si/sub 1-z/Ge/sub z/ (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. /spl sim/ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. /spl sim/ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.

Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

The impact of different processing factors on the low-frequency (LF) noise of nMOSFETs fabricated in strained-silicon (SSi) substrates will be described. It is shown that the use of an SSi substrate can yield improved LF noise performance compared with standard Czochralski silicon material. This is demonstrated for both full-wafer and selective epitaxial SSi material. The lower 1/f noise points to an improved gate oxide quality, i.e., with a lower interface and bulk defect density, and is correlated with the low-field mobility or transconductance of the transistors. At the same time, it will be demonstrated that there exist defect-related LF noise mechanisms, which generally give rise to excess generation-recombination (GR) noise. Associated with this GR noise, a degradation of either the OFF-state leakage current or the mobility (transconductance) of the devices is observed. It is clear that noise is a sensitive parameter to local defectiveness and may be a useful tool for both materials' characterization and the analysis of processing-related device degradation mechanisms.

Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates

The impact of processing factors such as ion implantation and rapid thermal annealing on mobility enhancement in strained-Si n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) has been investigated. Long-channel strained-Si and bulk n-MOSFETs were fabricated with various channel-region implant doses and thermal budgets. Neutral Si and Ge species were used to study the impact of the implant damage on mobility separately from ionized impurity scattering effects. Electron mobility enhancement is shown to degrade considerably when the implant dose is above a critical dose for a given thermal budget. Transmission electron microscopy, secondary ion mass spectrometry and Raman spectroscopy were used to investigate the mobility degradation mechanisms. Residual implant damage and implant damage enhanced Ge up-diffusion into the Si are shown to be responsible for the mobility degradation. Two-dimensional damage simulations of 30-nm scale MOSFETs are used to examine potential technological implications of these findings.

Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si N-channel MOSFETs

The retention time characteristics in DRAM cells are strongly influenced by various leakage mechanisms near the storage node junction. In this work, we present a full three-dimensional analysis of stress distributions in and around the active area of high-density memory cells. We use a combination of high-resolution metrology analysis and 3D numerical modeling to provide quantitative estimates. Since shallow - trench isolation (STI) process used in high-density cells is one of the major contributors to stress, we study the effects of various materials used to fill the trench. Our electron diffraction contrast (EDC) methodology provides a spatial resolution on the order of 10 nm with sensitivity on of the order of tens of MPa and therefore useful for the analysis of scaled high density memory cells.

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Three-Dimensional Characterization and Modeling of Stress Distribution in High-Density DRAM Memory Cells

Strained-Si based Field Effect Transistors (FETs) have enabled improvement of carrier transport in Metal Oxide Semiconductor (MOS)-based devices, both in the ON state of the device and in the sub-threshold region. This leads to devices with higher ratios of on-to-off current, improvements in the device sub-threshold slope, lower voltage operation, and carrier mobility enhancement. However, in order to understand the fundamental physics of these devices, it is important to address the stress conditions of the strained-Si channel layers after device processing, particularly after the ion-implantation process. In this work, we have studied Si+ self ion-implantation and thermally annealed strained-Si channel layers in n-MOSFETs. It has been observed that the density of defects in the strained-Si layer depends upon implant dose as well as thermal treatment. Using energy dispersive spectroscopy (EDS) spectra, it is found that Ge is present in the strained Si layer when analyzed after Si+ implantation and rapid thermal annealing. The presence of Ge in the strained Si channel layer causes relaxation of strain. This is verified by Convergent Beam Electron Diffraction (CBED) by measuring the lattice constant of the strained channel. It is concluded that electron mobility enhancements can be degraded in n- MOSFETs due to presence of both Ge up-diffusion and defects.

https://www.cambridge.org/core/services/aop-cambridge-core/content/view/S1946427400112850

Jian Li

Papers

Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si N-channel MOSFETs

Three-Dimensional Characterization and Modeling of Stress Distribution in High-Density DRAM Memory Cells

Characterization of Ultrathin Strained-Si Channel Layers of n-MOSFETs Using Transmission Electron Microscopy