Showing papers by "Jose Silva-Martinez published in 2006"

A Highly Linear Low-Noise Amplifier

Abstract: A low-noise amplifier (LNA) that achieves high third-order input intercept point (IIP3) at RF frequencies using a nonlinearity cancellation technique is proposed. The circuit tackles the problem of the effect of the second-order nonlinearity on IIP3 at RF frequencies. The circuit functionality is analyzed using Volterra series. The linear LNA was designed and fabricated in a TSMC 0.35-mum CMOS process. An IIP3 of +21 dBm was achieved with a gain of 11.5 dB, noise figure of 2.95 dB, and a power consumption of 9 mA at 2.5 V

Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters

Abstract: Recent progress of wide-band communication systems demands high-frequency circuits. Conventionally, the linearity of the operational transconductance amplifier and capacitor (OTA-C) has been analyzed using Taylor series expansion. Unfortunately, this approach does not predict the frequency-dependent linearity degradation. Thus, to properly design linearized OTAs, the frequency dependence of these coefficients must be determined. In this paper, we present a frequency-dependent harmonic-distortion analytical method applied to a linear-enhanced OTA. This OTA, which is suitable for high-frequency operation, uses three linearization techniques simultaneously: 1) attenuation through floating-gate MOS transistors; 2) source degeneration; and 3) polynomial cancellation techniques. By using the harmonic-distortion analysis, some properties on the performance of OTA are used to improve the performance of OTA-C based circuits at high frequencies. A 0.5-mum CMOS OTA simulation and experimental results are shown to verify the harmonic-distortion analytical method

Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching

Abstract: An ultrahigh-speed fully differential charge pump with minimum current mismatch and variation is proposed in this brief. A mismatch suppression circuit is employed to minimize the mismatch between the charging and discharging currents, which minimizes the steady-state phase error in a phase-locked loop (PLL). A variation suppression circuit is proposed to minimize output current variation with the change of output voltage, which reduces the variation of the bandwidth in a PLL. Techniques are proposed to suppress both low-speed glitches and high-speed glitches in the output current to allow glitch-free operation of the charge pump with ultrafast input pulses. The differential charge pump is designed and simulated under the power supply of 3.3 V in TSMC 0.35-mum CMOS technology to verify the effectiveness of the proposed techniques

A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz

Abstract: A 550-MHz linear-phase low-pass continuous-time filter is described. The operational transconductance amplifier (OTA) is based on complementary differential pairs in order to achieve high-frequency operation. A common-mode feedback (CMFB) based on a Class AB amplifier with improved stability at high frequencies is introduced. Results for the stand alone OTA show a unity gain frequency of 1 GHz while the excess phase is less than 5/spl deg/. The filter is based on G/sub m/-C biquads and achieves IM3 <-40 dB for a two-tone input signal of -10 dBm each. The power consumption of the fourth-order filter is 140 mW from supply voltages of /spl plusmn/1.65 V. The chip was fabricated in a standard 0.35-/spl mu/m CMOS technology.

An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing

Abstract: Current and future integrated systems demand cost-effective test solutions. In response to that need, this work presents a very compact mixed-signal test system. It performs the characterization of the magnitude and phase responses over frequency at multiple nodes of an analog circuit. The control inputs and output of this system are digital, enabling the test of the analog components in a system-on-chip (SoC) or system-in-package (SiP) through a low-cost digital automatic test equipment. Robust and area-efficient building blocks are proposed for the implementation of the test system, including a linearized analog multiplier for accurate magnitude and phase detection, a wide tuning range voltage-controlled oscillator and a low-power algorithmic analog-to-digital converter. Their individual design considerations and performance results are presented. A complete prototype in TSMC CMOS 0.35-mum technology employs only 0.3mm2 of area. The operation of this test system is demonstrated by performing frequency response characterizations up to 130 MHz at various nodes of two different fourth-order continuous-time filters integrated in the same chip

A High-Frequency Transconductor Using a Robust Nonlinearity Cancellation

Abstract: This brief deals with the design of a linear operational transconductance amplifier (OTA) intended for high-frequency continuous-time filters. Three source-degenerated differential pairs are used to reduce the third-order distortion components regardless of process parameter tolerances and bias current. Experimental results for an OTA fabricated in the TSMC 0.35-mum CMOS process are presented and compared with recently reported topologies. Draining 2.8 mA from a single supply voltage of 3.3 V, the transconductor achieves IM3<-70 dB for a two-tone input signal of 1.3 Vpp measured at 70 MHz. The input referred noise density is only 7 nV/radicHz, leading to an SNR of 75 dB

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

Abstract: A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-mum CMOS process; filter's area is 0.84 mm2

Quasi Rail-to-Rail Very Low-Voltage OPAMP With a Single pMOS Input Differential Pair

Abstract: In this brief, a quasi-rail-to-rail low-voltage operational amplifier (VDD-VSS-VDSATP-VDSATN ) is introduced. A common-mode adapter that uses the common-mode voltage present at the common-source node of the available differential pair to accommodate the large common-mode input signal is proposed. The common-mode adapter operates properly at 300 kHz while driving a load capacitor of 15 pF and employs only 95 muW of static power. The amplifier was fabricated in a standard AMI 0.5-mum CMOS process (Vtn=0.7 V and Vtp=-0.9 V) and achieves an IM3 of - 48 dB at 300 kHz for a two-tone input signal of 0.8 Vpk-pk. A 1-V total supply voltage was used

A carrier frequency generator for multi-band UWB radios

Abstract: A fast-switching carrier frequency generator for multi-band UWB radios is presented. It generates 11 carrier frequencies in quadrature in the range of 3.7-10GHz from a single frequency source. The architecture consists of a series of dividers, single sideband mixers with filtering and multiplexers. The IC is implemented in a 0.25/spl mu/m SiGe BiCMOS technology and measured in a QFN package. With an active area of 2.2 /spl times/ 1.9mm/sup 2/ the system draws 75mA of current from a 3V supply.

An 11-Band 3.4 to 10.3 GHz MB-OFDM UWB Receiver in 0.25/spl mu/m SiGe BiCMOS

Abstract: An 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB is implemented in a 0.25mum BiCMOS process. It includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The packaged IC mounted on FR-4 substrate provides maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply

Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends - An Overview

Abstract: This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in self-provided (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present test cost reduction requirements and techniques from a circuit design perspective. One promising approach for the test of fully-integrated RF transceiver front-ends with on-chip loopback and strategically placed power detectors along the RF signal path will be discussed as a demonstrative example of the presented concepts. The main focus in this paper is on reported work that is relevant to improvement of test coverage and cost reduction for on-wafer functional test with minimal area overhead and test time.

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

Abstract: A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.

A 10.7-MHz Sixth-Order SC Ladder Filter in

Abstract: A sixth-order 10.7-MHz bandpass switched-capac- itor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance ampli- fier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter buffer) third-intermodulation (IM3) distortion is less than dB for a two-tone input signal of -dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35- m CMOS process; filter's area is 0.84 mm .