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Design Of Analog Cmos Integrated Circuits

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Detection, Estimation, and Modulation Theory

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

Low-IF topologies for high-performance analog front ends of fully integrated receivers

Direct-conversion microwave Doppler radar can be used to detect cardiopulmonary activity at a distance. One challenge for such detection in single channel receivers is demodulation sensitivity to target position, which can be overcome by using a quadrature receiver. This paper presents a mathematical analysis and experimental results demonstrating the effectiveness of arctangent demodulation in quadrature receivers. A particular challenge in this technique is the presence of dc offset resulting from receiver imperfections and clutter reflections, in addition to dc information related to target position and associated phase. These dc components can be large compared to the ac motion-related signal, and thus, cannot simply be included in digitization without adversely affecting resolution. Presented here is a method for calibrating the dc offset while preserving the dc information and capturing the motion-related signal with maximum resolution. Experimental results demonstrate that arctangent demodulation with dc offset compensation results in a significant improvement in heart rate measurement accuracy over quadrature channel selection, with a standard deviation of less than 1 beat/min

Arctangent Demodulation With DC Offset Compensation in Quadrature Doppler Radar Receiver Systems

This paper describes a background calibration technique that linearizes pipelined ADCs by correcting for errors in the digital domain. This also relaxes the requirements for the analog components and enables power and area savings. The calibration technique doesn't require a separate reference ADC that samples the input, nor the generation of digital correlation signals or extra analog calibration components. The calibration technique is robust and easily implementable in any digital technology. The implementation of the digital calibration algorithm requires minimal digital resources and less than 1% of the overall ADC power consumption.

Efficient calibration scheme for high-resolution pipelined ADCs

Emerging wireless communication services require the efficient use of available spectrum and improved co-existence of different standards placed in adjacent frequency bands. Co-existence with leakage from primary users in adjacent channels, which falls in the band of interest, is a primary concern for existing and emerging technologies. In this paper, a mixed signal IC technique based on direct sequence spread spectrum is proposed to improve co-existence of radar systems with commercial wireless communication systems. A sinusoid-like pseudo-random sequence is introduced to reduce leakage from radar systems into adjacent channels. The proposed approach reduces the radar signal leakage on adjacent channels by about 22dB when compared with the conventional binary pseudo-random sequence. The proposed technique randomizes narrow and wideband systematic in-band interference, after which interference power can be effectively attenuated through averaging techniques. Experimental results from a 40nm CMOS technology modulator/demodulator prototype demonstrates the feasibility of the proposed architecture. The modulator and demodulator system requires a silicon area of 0.0459mm2 and consumes 4.33mW in total.

An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference

This chapter deals with the design of DS modulators for wireless applications. Two case studies are presented to discuss general design issues and to give insights into the possibilities that exist for solving contemporary challenges with time-domain processing techniques. The first architecture employs a time-to-digital converter based on pulse-width. Its time-based single-level DAC achieves linear multi-bit feedback, leading to the DS modulator’s dynamic range of 68 dB. The second architecture employs a 7-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and DAC. Fabricated in a 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW, and occupies a die area of 2.6 mm2. This modulator has a measured SFDR of 78 dB and in-band IM3 under −72 dB at −2dBFS.

Wideband Continuous-Time Multi-Bit Delta-Sigma ADCs

In high-Q, low-sampling rate switched-capacitor filters the main limitation comes from the capacitance spread. A secondary clock, that averages at an integer fraction of the main clock signal, is used to reduce the capacitance spread by a factor of N, relaxing the operational transconductance amplifier (OTA) requirements. The secondary clock is pulse position modulated to reduce the power of alias components. Experimental results obtained from a second-order bandpass switched-capacitor filter breadboard prototype are shown.

A high-Q, switched-capacitor filter with reduced capacitance spread using a randomized nonuniform sampling technique

This paper presents two low-power demultiplexers working at 25 Gbps and 5 Gbps input data rate respectively The 25 Gbps demultiplexer consumes only 68 mW power dissipation The 5 Gbps demultiplexer consumes 425 mW power dissipation The two demultiplexers are implemented in TSMC 035 /spl mu/m CMOS technology They are built on the same chip sharing input and output ports The power supply of the chip is 25 V The demultiplexers are designed to be modules for optical communication receiver systems

Jose Silva-Martinez

Papers

Efficient calibration scheme for high-resolution pipelined ADCs

An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference

Wideband Continuous-Time Multi-Bit Delta-Sigma ADCs

A high-Q, switched-capacitor filter with reduced capacitance spread using a randomized nonuniform sampling technique

6.8 mW 2.5 Gb/s and 42.5 mW 5 Gb/s 1:8 CMOS demultiplexers