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Design Of Analog Cmos Integrated Circuits

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Detection, Estimation, and Modulation Theory

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

Low-IF topologies for high-performance analog front ends of fully integrated receivers

Direct-conversion microwave Doppler radar can be used to detect cardiopulmonary activity at a distance. One challenge for such detection in single channel receivers is demodulation sensitivity to target position, which can be overcome by using a quadrature receiver. This paper presents a mathematical analysis and experimental results demonstrating the effectiveness of arctangent demodulation in quadrature receivers. A particular challenge in this technique is the presence of dc offset resulting from receiver imperfections and clutter reflections, in addition to dc information related to target position and associated phase. These dc components can be large compared to the ac motion-related signal, and thus, cannot simply be included in digitization without adversely affecting resolution. Presented here is a method for calibrating the dc offset while preserving the dc information and capturing the motion-related signal with maximum resolution. Experimental results demonstrate that arctangent demodulation with dc offset compensation results in a significant improvement in heart rate measurement accuracy over quadrature channel selection, with a standard deviation of less than 1 beat/min

Arctangent Demodulation With DC Offset Compensation in Quadrature Doppler Radar Receiver Systems

The design and implementation of a fully integrated complementary metal-oxide-semiconductor (CMOS) sixth-order 2.4 Hz low-pass fitter (LPF) for medical applications is presented. For the implementation of large-time constants both linearized operational transconductance amplifiers with reduced transconductance and impedance scalers schemes for grounded capacitors are employed. Experimental results for the filter have shown a dynamic range (DR) of 60 dB, while the harmonic distortion components are below -50 dB. The power consumption for the filter is below 10 /spl mu/W, the power supply is /spl plusmn/1.5 V, and the active area is 1 mm/sup 2/. The filter was fabricated in a double poly double metal 0.8 /spl mu/m CMOS process.

/pdf/a-60-db-dynamic-range-cmos-sixth-order-2-4-hz-low-pass-4yb5at7oe7.pdf

A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications

A family of CMOS operational transconductance amplifiers (OTAs) has been designed for very small G/sub m/'s (of the order of nanoamperes per volt) with transistors operating in moderate inversion. Several OTA design schemes such as conventional, using current division, floating-gate, and bulk-driven techniques are discussed. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area, and signal-to-noise ratio. The transconductance amplifiers have been fabricated in a 1.2-/spl mu/m n-well CMOS process and operate at a power supply of 2.7 V. Chip test results are in good agreement with theoretical results.

Transconductance amplifier structures with very small transconductances: a comparative design approach

The design of a 2.4-GHz fully integrated /spl Sigma//spl Delta/ fractional-N frequency synthesizer in a 0.35-/spl mu/m CMOS process is presented. The design focuses on the prescaler and the loop filter, which are often the speed and the integration bottlenecks of the phase-locked loop (PLL), respectively. A 1.5-V 3-mW inherently glitch-free phase-switching prescaler is proposed. It is based on eight lower frequency 45/spl deg/-spaced phases and a reversed phase-switching sequence. The large integrating capacitor in the loop filter was integrated on chip via a simple capacitance multiplier that saves silicon area, consumes only 0.2 mW, and introduces negligible noise. The synthesizer has a 9.4% frequency tuning range from 2.23 to 2.45 GHz. It dissipates 16 mW and takes an active area of 0.35 mm/sup 2/ excluding the 0.5-mm/sup 2/ digital /spl Sigma//spl Delta/ modulator.

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V/sub p-p/). The complete system operates with supply voltages of +or-2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5- mu m n-well CMOS process. >

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning

This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed. The PSR performance is improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. The effectiveness of the PSR enhancement technique is experimentally verified with an LDO that was fabricated in a 0.18 μm CMOS technology with a power supply of 1.8 V. The active core chip area is 0.14 mm2, and the entire proposed LDO consumes 80 μA of quiescent current during operation mode and 55 μA of quiescent current in standby mode. It has a drop-out voltage of 200 mV when delivering 50 mA to the load. The measured PSR is better than -56 dB up to 4 MHz when delivering a current of 50 mA. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively.

Jose Silva-Martinez

Papers

A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications

Transconductance amplifier structures with very small transconductances: a comparative design approach

A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning

External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range