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Design Of Analog Cmos Integrated Circuits

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Detection, Estimation, and Modulation Theory

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

Low-IF topologies for high-performance analog front ends of fully integrated receivers

Direct-conversion microwave Doppler radar can be used to detect cardiopulmonary activity at a distance. One challenge for such detection in single channel receivers is demodulation sensitivity to target position, which can be overcome by using a quadrature receiver. This paper presents a mathematical analysis and experimental results demonstrating the effectiveness of arctangent demodulation in quadrature receivers. A particular challenge in this technique is the presence of dc offset resulting from receiver imperfections and clutter reflections, in addition to dc information related to target position and associated phase. These dc components can be large compared to the ac motion-related signal, and thus, cannot simply be included in digitization without adversely affecting resolution. Presented here is a method for calibrating the dc offset while preserving the dc information and capturing the motion-related signal with maximum resolution. Experimental results demonstrate that arctangent demodulation with dc offset compensation results in a significant improvement in heart rate measurement accuracy over quadrature channel selection, with a standard deviation of less than 1 beat/min

Arctangent Demodulation With DC Offset Compensation in Quadrature Doppler Radar Receiver Systems

This brief deals with the design of a linear operational transconductance amplifier (OTA) intended for high-frequency continuous-time filters. Three source-degenerated differential pairs are used to reduce the third-order distortion components regardless of process parameter tolerances and bias current. Experimental results for an OTA fabricated in the TSMC 0.35-mum CMOS process are presented and compared with recently reported topologies. Draining 2.8 mA from a single supply voltage of 3.3 V, the transconductor achieves IM3<-70 dB for a two-tone input signal of 1.3 Vpp measured at 70 MHz. The input referred noise density is only 7 nV/radicHz, leading to an SNR of 75 dB

A High-Frequency Transconductor Using a Robust Nonlinearity Cancellation

Built-in self test techniques for local oscillator phase noise, RF front-end circuits, baseband building blocks and transceiver loop-back are described. CMOS implementation of integrated RF test components, including RF detectors and phase discriminators are introduced. These devices eliminate the need for expensive external test equipment. The presented test strategies can also be used at wafer-level for fault diagnosis, localization and yield estimation. Silicon characterization results verifying most of these techniques are provided.

Built-in Self Test of RF Transceiver SoCs: from Signal Chain to RF Synthesizers

In this paper, a 3GHz-10GHz ultra wideband (UWB) low noise amplifier (LNA) typology is proposed. The broadband matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal noise figure (NF), good linearity, and the lower power consumption are also desired. The common gate input stage with the 3rd order Butterworth filter configuration is used in the proposed LNA to achieve the broadband input matching. The flat gain of the LNA is achieved by the combination of the inductor peaking load and the shunt inductor insertion between the cascade stages of LNA. The LNA is designed in the standard 0.18mum CMOS technology. It achieved 14.5~15.3dB gain from 3GHz to 10GHz and 3.43dBm IIP3 in 5GHz, operates from 1.8V power supply, and dissipates 4.3mW without the output buffer

A 3GHz-10GHz common gate ultrawideband low noise amplifier

A sixth-order 10.7-MHz bandpass switched-capacitor filter based on a double terminated ladder filter is presented. The filter uses a multipath operational transconductance amplifier (OTA) that presents both better accuracy and higher slew rate than previously reported Class-A OTA topologies. Design techniques based on charge cancellation and slower clocks are used to reduce the overall capacitance from 782 down to 219 unity capacitors. The filter's center frequency and bandwidth are 10.7 MHz and 400 kHz, respectively, and a passband ripple of 1 dB in the entire passband. The quality factor of the resonators used as filter terminations is around 32. The measured (filter + buffer) third-intermodulation (IM3) distortion is less than -40 dB for a two-tone input signal of +3-dBm power level each. The signal-to-noise ratio is roughly 58 dB while the IM3 is -45 dB; the power consumption for the standalone filter is 42 mW. The chip was fabricated in a 0.35-mum CMOS process; filter's area is 0.84 mm2

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

This paper presents a quadrature voltage-controlled oscillator (QVCO) employing a proposed dynamic current-clipping coupling technique to provide around 90° phase shift in the coupling paths. The phase shift given by the coupling network not only improves the phase noise, but also desensitizes the phase error to component mismatches in the QVCO. The coupling network furthermore reduces the noise injected into the LC tank at the most vulnerable time (zero crossing points). The proposed current-clipping coupling allows the use of a strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1-MHz offset from a 5-GHz carrier. The QVCO consumes 4.2 mW from a 1-V power supply, resulting in an outstanding figure of merit of 189 dBc/Hz.

Jose Silva-Martinez

Papers

A High-Frequency Transconductor Using a Robust Nonlinearity Cancellation

Built-in Self Test of RF Transceiver SoCs: from Signal Chain to RF Synthesizers

A 3GHz-10GHz common gate ultrawideband low noise amplifier

A 10.7-MHz sixth-order SC ladder filter in 0.35-/spl mu/m CMOS technology

A 5-GHz CMOS LC Quadrature VCO With Dynamic Current-Clipping Coupling to Improve Phase Noise and Phase Accuracy