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Design Of Analog Cmos Integrated Circuits

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Detection, Estimation, and Modulation Theory

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

Low-IF topologies for high-performance analog front ends of fully integrated receivers

Direct-conversion microwave Doppler radar can be used to detect cardiopulmonary activity at a distance. One challenge for such detection in single channel receivers is demodulation sensitivity to target position, which can be overcome by using a quadrature receiver. This paper presents a mathematical analysis and experimental results demonstrating the effectiveness of arctangent demodulation in quadrature receivers. A particular challenge in this technique is the presence of dc offset resulting from receiver imperfections and clutter reflections, in addition to dc information related to target position and associated phase. These dc components can be large compared to the ac motion-related signal, and thus, cannot simply be included in digitization without adversely affecting resolution. Presented here is a method for calibrating the dc offset while preserving the dc information and capturing the motion-related signal with maximum resolution. Experimental results demonstrate that arctangent demodulation with dc offset compensation results in a significant improvement in heart rate measurement accuracy over quadrature channel selection, with a standard deviation of less than 1 beat/min

Arctangent Demodulation With DC Offset Compensation in Quadrature Doppler Radar Receiver Systems

A modification to the conventional folded cascode transconductance amplifier is proposed. The proposed amplifier has the benefit of achieving a given set of design specifications while consuming a fraction of the power compared to the conventional folded cascode. Moreover, the proposed modification is robust even for low voltage applications.

Enhancing general performance of folded cascode amplifier by recycling current

This paper presents a sixth-order bandpass ΣΔ modulator with 10 MHz bandwidth and 200 MHz center frequency suitable for high-IF applications. The fs/4 modulator employs an 800 MHz clock frequency and uses an active RC loop filter implemented with three-stage linearized operational amplifiers achieving more than 50 dB gain at 200 MHz. Furthermore, a calibration technique is proposed to compensate for process-voltage-temperature (PVT) variations, which involves measurement and optimization of the noise transfer function by injecting two auxiliary tones at the quantizer input. The modulator achieves 68.4 dB peak SNDR measured in 10 MHz bandwidth and IM3 of -73.5 dB at -2 dBr input signal. Fabricated in a vanilla 0.18 μm CMOS technology, the modulator consumes 160 mW (static + dynamic power) and occupies an active silicon area of 2.5 mm2.

A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth

A fourth-order continuous-time LC bandpass sigma-delta ADC is designed using a new architecture with only non-return-to-zero feedback DACs to mitigate problems associated with clock jitter, along with individual control of coefficients in the noise transfer function. The ADC performs direct digitization of RF signals around 950-MHz center frequency with a 3.8-GHz clock. The operation of the proposed ADC architecture is examined in detail and extra design parameters are introduced to enhance the operating range and improve the stability of the ADC. Measurement results of the ADC, implemented in IBM 0.25-mum SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz, while consuming 75 mW of power from plusmn1.25-V supply

A 63 dB SNR, 75-mW Bandpass RF $\Sigma\Delta$ ADC at 950 MHz Using 3.8-GHz Clock in 0.25- $\mu{\hbox {m}}$ SiGe BiCMOS Technology

This paper deals with the design of very small ac transconductance voltage to current transducers intended for the design of low frequency continuous-time filters, very large resistors and other applications. The first type of Operational Transconductance Amplifiers (OTA) is based on a triode biased transistor and a current division technique. The second one uses partial positive feedback which allows to reduce transistor dimensions but the sensitivity to transistor mismatches increases. The proposed techniques can be used for the design of high-order low frequency IC filters, ladder or based on biquads, with moderated transistor dimensions while the dynamic range-cutoff frequency performance is comparable to previously reported structures. A 10 Hz third order lowpass ladder filter has been designed with these techniques, and it shows a dynamic range of 62 dB. Besides, a novel biasing technique for capacitive sources coupled preamplifiers is proposed. Experimental results for a prototype, fabricated in a 1.2 μm CMOS process, have shown very low distortion components (THD< 1 level below 15 μ V_RMS and dynamic range of 63 dB. The power consumption is only 10 μwatts and the supply voltages are ± 1.5 volts.

IC Voltage to Current Transducers with Very Small Transconductance

This work presents an analysis on frequency planning and synthesis for multiband (MB) orthogonal frequency-division multiplexing (OFDM) ultra-wideband (UWB) radios operating in the range of 3.1-10.6 GHz. The most important specifications for the frequency synthesizer in an MB-OFDM UWB transceiver are provided. A synthesizer architecture for an existing frequency plan is introduced along with a discussion on its performance and implementation. An alternative frequency plan and its corresponding synthesizer architecture are also proposed. It is shown how this modified frequency plan leads to a significant simplification in the synthesizer realization. The feasible performance of both synthesizer architectures is evaluated through macromodel simulations using realistic models for the building blocks. Finally, system-level simulation results showing the impact of synthesizer spurs on the bit error rate performance of an MB-OFDM UWB receiver in the presence of interferers are provided. The presented results and discussion provide valuable insight for the implementation of a 3.1-10.6-GHz UWB synthesizer.

Jose Silva-Martinez

Papers

Enhancing general performance of folded cascode amplifier by recycling current

A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth

A 63 dB SNR, 75-mW Bandpass RF $\Sigma\Delta$ ADC at 950 MHz Using 3.8-GHz Clock in 0.25- $\mu{\hbox {m}}$ SiGe BiCMOS Technology

IC Voltage to Current Transducers with Very Small Transconductance

Frequency planning and synthesizer architectures for multiband OFDM UWB radios