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Design Of Analog Cmos Integrated Circuits

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Detection, Estimation, and Modulation Theory

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

Low-IF topologies for high-performance analog front ends of fully integrated receivers

Direct-conversion microwave Doppler radar can be used to detect cardiopulmonary activity at a distance. One challenge for such detection in single channel receivers is demodulation sensitivity to target position, which can be overcome by using a quadrature receiver. This paper presents a mathematical analysis and experimental results demonstrating the effectiveness of arctangent demodulation in quadrature receivers. A particular challenge in this technique is the presence of dc offset resulting from receiver imperfections and clutter reflections, in addition to dc information related to target position and associated phase. These dc components can be large compared to the ac motion-related signal, and thus, cannot simply be included in digitization without adversely affecting resolution. Presented here is a method for calibrating the dc offset while preserving the dc information and capturing the motion-related signal with maximum resolution. Experimental results demonstrate that arctangent demodulation with dc offset compensation results in a significant improvement in heart rate measurement accuracy over quadrature channel selection, with a standard deviation of less than 1 beat/min

Arctangent Demodulation With DC Offset Compensation in Quadrature Doppler Radar Receiver Systems

A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process. The key feature of the proposed receiver front-end is a single low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference and outstanding linearity. We employ a broadband common-gate (CG) LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance. A LNTA load impedance boosting technique suppresses noise-amplification due to TIA, commonly found in passive mixers. The core circuit (RF and baseband signal path) consumes only 13 mW, and the prototype receiver achieves >22.4-dB conversion gain, dB NF, and ≥ -1.5 dBm IIP3 from 1.4 to 5.2 GHz. Maximum conversion gain of 24.3 dB and minimum NF of 6.5 dB are achieved at 1.4 and 2 GHz, respectively. The chip active area is 1.1 mm 2 with the entire RF signal path operated from a 1.2-V supply. The LO portion is biased from a 1.5-V supply.

Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications

A CMOS 80-200-MHz fourth-order continuous-time 0.05/spl deg/ equiripple linear phase filter with an automatic frequency tuning system is presented. An operational transconductance amplifier based on transistors operating in triode region is used and a circuit that combines common-mode feedback, common-mode feedforward, and adaptive bias is introduced. The chip was fabricated in a 0.35-/spl mu/m process; filter experimental results have shown a total harmonic distortion less than -44 dB for a 2-V/sub pp/ differential input with a single 2.3-V power supply. The group delay ripple is less than 4% for frequencies up to 1.5 f/sub c/. The frequency tuning error is below 5%.

A 2-V/sub pp/ 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning

This work presents a receiver implementation for MB-OFDM UWB communication that enables 11 bands of operation covering 78% of the spectrum licensed by the FCC. First, important system-level considerations are discussed with basis on the specifications from the MB-OFDM standard. Next, the different circuit techniques employed in the implementation of the receiver are described. For the LNA design, a wideband impedance match network that takes into account the package components is introduced. A notch filter embedded in the LNA and its tuning mechanism are proposed to attenuate the interference from devices operating in the U-NII band from 5.15 to 5.35GHz. Based on the results of a recent investigation on frequency planning for MB-OFDM radios, a compact 11-band fast-hopping synthesizer implementation is proposed for the receiver. The 264-MHz baseband section consists of a linear phase low pass filter and a programmable gain amplifier; it presents an in-band group delay variation of less than 0.6 ns and 42 dB of gain in steps of 2 dB. The IC is fabricated in a 0.25-mum SiGe BiCMOS process, placed in a QFN package and mounted on FR-4 substrate for its characterization. Measurement results show a receiver gain of 78-67 dB and NF of 5-10 dB across the 11 bands from 3-10 GHz, while consuming 114 mA from a 2.5-V supply

An 11-Band 3–10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication

A third-order CT ΔΣ ADC that replaces the multi-bit quantizer and feedback DAC by a pulsewidth modulation (PWM) generator and time-to-digital converter (TDC) is implemented in 65 nm CMOS technology. The TDC provides a 50-level binary output code and a time-quantized feedback pulse to the modulator. It is shown that the TDC can achieve 11 bit linearity in time steps without calibration or dynamic element matching. The modulator achieves 68 dB DR in 20 MHz BW, consumes 10.5 m W and occupies 0.15 mm2.

A Continuous Time Multi-Bit $\Delta \Sigma$ ADC Using Time Domain Quantizer and Feedback Element

A general description of nonlinearities in pseudo differential operational transconductance amplifiers (OTA) with common-mode feedback (CMFB) is introduced. The effects of CMFB nonlinearities on the differential signals are evaluated and design tradeoffs including nonidealities are determined. A practical pseudo differential fully balanced fully symmetric OTA architecture with common-mode feedforward (CMFF) is used as a case study to probe the theory. The OTA has an inherent common-mode detector; hence, the CMFB circuit is efficiently implemented. The OTA is used to implement a 100-MHz fourth-order linear-phase OTA-C filter.

Jose Silva-Martinez

Papers

Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications

A 2-V/sub pp/ 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning

An 11-Band 3–10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication

A Continuous Time Multi-Bit $\Delta \Sigma$ ADC Using Time Domain Quantizer and Feedback Element

Nonlinear effects in pseudo differential OTAs with CMFB