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Design Of Analog Cmos Integrated Circuits

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Detection, Estimation, and Modulation Theory

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

Low-IF topologies for high-performance analog front ends of fully integrated receivers

Direct-conversion microwave Doppler radar can be used to detect cardiopulmonary activity at a distance. One challenge for such detection in single channel receivers is demodulation sensitivity to target position, which can be overcome by using a quadrature receiver. This paper presents a mathematical analysis and experimental results demonstrating the effectiveness of arctangent demodulation in quadrature receivers. A particular challenge in this technique is the presence of dc offset resulting from receiver imperfections and clutter reflections, in addition to dc information related to target position and associated phase. These dc components can be large compared to the ac motion-related signal, and thus, cannot simply be included in digitization without adversely affecting resolution. Presented here is a method for calibrating the dc offset while preserving the dc information and capturing the motion-related signal with maximum resolution. Experimental results demonstrate that arctangent demodulation with dc offset compensation results in a significant improvement in heart rate measurement accuracy over quadrature channel selection, with a standard deviation of less than 1 beat/min

Arctangent Demodulation With DC Offset Compensation in Quadrature Doppler Radar Receiver Systems

A novel ultrafast and low-cost pipelined analog-to-digital converter (ADC) testing and calibration method is proposed. The ADC nonlinearities are modeled as segmented parameters with interstage gain errors. During the test phase, a pure sine wave is sent as input and the model parameters are estimated from the output data with the system identification method. Significantly, fewer samples are required when compared to traditional histogram testing. The modeled errors are then removed from the digital output codes during the calibration phase. Extensive simulations have been run to verify the correctness and robustness of the proposed method. With just 4000 samples, a 12-bit ADC can be accurately tested and calibrated to achieve less than 1 least significant bit (LSB) integral nonlinearity (INL). Measurement results show that the ADC effective number of bits (ENOB) is improved from 9.7to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by 20 dB after calibration. The chip is fabricated in 40-nm technology and consumes 10.71 mW at a sampling rate of 125 MS/s.

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method

In this paper a Switched-Capacitor (SC) architecture for the processing of binary input signals is presented. The architecture is especially useful for the realization of Finite Impulse Response (FIR) filters. A 23-th order Raised-Cosine (RC) filter employing 11 capacitors is designed. The filter has been simulated using a 0.8 /spl mu/m analog CMOS process. Hspice results have shown the feasibility of the proposed design technique.

SC implementation of FIR filters for digital communication systems

The effects of the finite operational amplifier gain-bandwidth product GB on the performance of an inverting switched-capacitor amplifier are presented. Limitations of the GB and the clock frequency fc=1/T as well as GB.T are determined.

Effects of finite operational amplifier gain-bandwidth product on a switched-capacitor amplifier

This paper deals with the effect of the transistor mismatches on the performance of Fully Differential Operational Transconductance Amplifiers (FDOTA). A simple macro model including transistor mismatches is proposed. From this model, the four transfer functions that determine the behavior of the FDOTA can be easily obtained. These transfer functions are further discussed and some clues in the design of high-performance FDOTAs are provided. Experimental results for a 6 /spl mu/A/V FDOTA fabricated in a 1.2 /spl mu/m CMOS process are in good agreement with the theoretical and simulated ones. >

Effect of the transistor mismatches on the performance of fully-differential OTAs

Future wireless devices will require extensive connectivity to accommodate several services, which means that the receivers must cover broader frequency bands. Therefore, on-chip analog-to-digital converters (ADCs) in multi-standard receivers not only demand increased signal-to-quantization-noise-ratio, but also more bandwidth for the conversion of the analog signals into the digital domain. This chapter briefly introduces a lowpass continuous-time ΣΔ ADC architecture that was developed for next generation broadband receiver applications. Rather than using multiple signal levels, a multi-bit digital-to-analog converter (DAC) realization based on a feedback signal with time-varying pulse duration was employed. This approach alleviates nonlinearity problems associated with typical multi-bit DACs. The chapter also contains an in-depth description of the corresponding 3-bit quantizer architecture with multi-phase clocking. The reference levels for this quantizer are adjustable to compensate for process variations after fabrication if the application necessitates fine resolution.

Jose Silva-Martinez

Papers

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method

SC implementation of FIR filters for digital communication systems

Effects of finite operational amplifier gain-bandwidth product on a switched-capacitor amplifier

Effect of the transistor mismatches on the performance of fully-differential OTAs

Multi-Bit Quantizer Design for Continuous-Time Sigma-Delta Modulators with Reduced Device Matching Requirements