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Design Of Analog Cmos Integrated Circuits

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Detection, Estimation, and Modulation Theory

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-IF receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-IF receiver has a topology which is closely related to the zero-IF receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-IF receiver, the implementation of a low-IF receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-IF receiver topology are introduced. Different low-IF receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique-a technique used in digital applications to the study of analog receiver front ends.

Low-IF topologies for high-performance analog front ends of fully integrated receivers

Direct-conversion microwave Doppler radar can be used to detect cardiopulmonary activity at a distance. One challenge for such detection in single channel receivers is demodulation sensitivity to target position, which can be overcome by using a quadrature receiver. This paper presents a mathematical analysis and experimental results demonstrating the effectiveness of arctangent demodulation in quadrature receivers. A particular challenge in this technique is the presence of dc offset resulting from receiver imperfections and clutter reflections, in addition to dc information related to target position and associated phase. These dc components can be large compared to the ac motion-related signal, and thus, cannot simply be included in digitization without adversely affecting resolution. Presented here is a method for calibrating the dc offset while preserving the dc information and capturing the motion-related signal with maximum resolution. Experimental results demonstrate that arctangent demodulation with dc offset compensation results in a significant improvement in heart rate measurement accuracy over quadrature channel selection, with a standard deviation of less than 1 beat/min

Arctangent Demodulation With DC Offset Compensation in Quadrature Doppler Radar Receiver Systems

A pipeline analog-to-digital converter (ADC) with high power efficiency is implemented in this paper. The ADC architecture consists of 3.5b, 3.5b, 3.5b, and 4b sub-ADCs. For the first three stages, a current-reuse technique is employed in the current mode multiplying digital-to-analog converters (MDACs). An operational transconductance amplifier (OTA) converts an input voltage into current; A current-steering DAC reuses the OTA bias current. The OTA and the DAC generate the sub-ADC residue in a current domain. As a result, both power consumption and thermal noise for the MDAC are reduced. A transimpedance amplifier (TIA) with a feedback resistor is utilized to convert the current signal to a voltage residue signal for the next stage. An off-chip calibration scheme is used to correct interstage gain and nonlinearity errors. The fabricated ADC achieves 68.1 dB signal-to-noise-and-distortion ratio (SNDR) and 82.3 dB spurious free dynamic range (SFDR) for a sinusoidal input at 4.17 MHz. The ADC operates at a maximum sampling frequency of 260 MHz. With an input signal at 123.129 MHz, the measured SNDR/SFDR are 66.3/78.22 dB, respectively. The total power consumption for the ADC running at maximum speed is 15.38 mW. Thus, the pipeline ADC achieves a 167.4 dB figure-of-merit (FoM). The chip was manufactured in a TSMC 40-nm CMOS process.

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

A compact and fully programmable Gaussian function circuit with temperature compensation is introduced. The programmability of the Gaussian circuit generator is carried out by using current sources. Hspice simulations for the proposed structure have shown deviations from the ideal Gaussian function below 3%. Breadboard results for the Gaussian circuit generator, in good agreement with the theoretical ones, are reported.

A fully-programmable temperature-compensated analogue circuit for Gaussian functions

Biquadratic programmable sc filters with additional flexibility and reduced total capacitance

A new topology for wideband multistage amplifiers (MA) is introduced. The proposed method uses active negative feedback in a chain of amplifiers to extend the bandwidth and improve gain-bandwidth product. The topology has several advantages such as having capability of widening bandwidth as the number of stage increases and enhancing bandwidth by several times that of the dominant pole of each stage. To verify the performance of topology, an 8-stage amplifier in 0.35 /spl mu/m CMOS was designed, where more than 2.8 GHz bandwidth and 40 dB gain were obtained from simulations.

Bandwidth enhancement of multi-stage amplifiers using active feedback

Design considerations for ultra-high frequency OTA-C filters are discussed. The effects of the OTA non-idealities on the precision of high-Q filters are accounted for. The parasitic capacitors produce center frequency deviations, and the finite OTA output resistance reduces the Q-factor while the parasitic poles introduce Q-enhancement. In this paper it is shown that the non-dominant pole effects are the most critical ones, hence the use of single-stage OTA's is a must. The effects of the parasitic capacitors on the filter's linearity are considered as well. Simulated results for a 2/sup nd/ order 500 MHz high-Q bandpass filter using a 0.35 /spl mu/m technology are reported.

Jose Silva-Martinez

Papers

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

A fully-programmable temperature-compensated analogue circuit for Gaussian functions

Biquadratic programmable sc filters with additional flexibility and reduced total capacitance

Bandwidth enhancement of multi-stage amplifiers using active feedback

Design issues for UHF OTA-C filter realizations