K
Kenneth J. Reyer
Researcher at IBM
Publications - 18
Citations - 93
Kenneth J. Reyer is an academic researcher from IBM. The author has contributed to research in topics: Signal & Clock signal. The author has an hindex of 6, co-authored 18 publications receiving 91 citations.
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Patent
Method and apparatus for implementing multiple column redundancy for memory
TL;DR: In this article, an apparatus for implementing multiple memory column redundancy within an individual memory array includes a plurality of memory array elements internally partitioned into at least a pair of subcolumn elements.
Journal ArticleDOI
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
Gregory J. Fredeman,Donald W. Plass,Abraham Mathews,Janakiraman Viraraghavan,Kenneth J. Reyer,Thomas J. Knips,Thomas R. Miller,Elizabeth L. Gerhard,Dinesh Kannambadi,Chris Paone,Dongho Lee,Daniel J. Rainey,Michael A. Sperling,Michael Whalen,Steven Burns,Rajesh R. Tummuru,Herbert L. Ho,Alberto Cestero,Norbert Arnold,Babar A. Khan,Toshiaki Kirihata,Subramanian S. Iyer +21 more
TL;DR: A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm2 deep-trench capacitor cell that enables a high voltage gain of a power-gated inverter at mid-level input voltage.
Patent
Write control circuitry and method for a memory array configured with multiple memory subarrays
TL;DR: In this paper, a write control circuitry and control method for a memory array configured with multiple memory subarrays is provided for a write controller that selectively enables a local write control signal to its associated memory subarray.
Patent
ABIST data compression and serialization for memory built-in self test of SRAM with redundancy
TL;DR: In this paper, a method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy is presented, which includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing outs.
Patent
Gated-feedback sense amplifier for single-ended local bit-line memories
TL;DR: In this paper, a single-ended input sense amplifier uses a pass device to couple the input local bit line to a global bit-line evaluation node, and the sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit line evaluation node.