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Kun Zhou

Researcher at China Academy of Engineering Physics

Publications -  58
Citations -  617

Kun Zhou is an academic researcher from China Academy of Engineering Physics. The author has contributed to research in topics: Trench & Breakdown voltage. The author has an hindex of 12, co-authored 58 publications receiving 469 citations. Previous affiliations of Kun Zhou include University of Electronic Science and Technology of China.

Papers
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Low on-Resistance SOI Dual-Trench-Gate MOSFET

Xiaorong Luo, +13 more
- 01 Feb 2012 - 
TL;DR: In this paper, a low specific onresistance (Ron,sp) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation.
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SiC Trench MOSFET With Integrated Self-Assembled Three-Level Protection Schottky Barrier Diode

Xuan Li, +11 more
- 01 Jan 2018 - 
TL;DR: In this article, a SiC trench MOSFET with integrated three-level protection (TLP) Schottky barrier diode (SBD), named ITS-TMOS, is proposed and investigated by simulation.
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Analytical Model and New Structure of the Variable- $k$ Dielectric Trench LDMOS With Improved Breakdown Voltage and Specific ON-Resistance

Kun Zhou, +3 more
- 20 Aug 2015 - 
TL;DR: In this article, a laterally double-diffused metal-oxide-semiconductor transistor with ultralow specific ON-resistance is proposed, and its analytical model for the breakdown voltage (BV) is presented.
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Ultralow ON-Resistance High-Voltage p-Channel LDMOS With an Accumulation-Effect Extended Gate

Xiaorong Luo, +6 more
- 06 May 2016 - 
TL;DR: In this paper, an ultralow specific ON-resistance pLDMOS with improved BV is proposed and investigated by simulation, which features an extended gate with accumulation effect over the drift region and a P+ floating layer (PFL) in the N-sub.
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Investigation and Failure Mode of Asymmetric and Double Trench SiC mosfet s Under Avalanche Conditions

Xiaochuan Deng, +9 more
- 17 Jan 2020 - 
TL;DR: In this article, the authors investigated the failure mechanisms of asymmetric and double trench SiC mosfet transistors under single-pulse unclamped inductive switching (UIS) stress.