M
Mamidala Jagadesh Kumar
Researcher at Indian Institute of Technology Delhi
Publications - 111
Citations - 4132
Mamidala Jagadesh Kumar is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: MOSFET & Threshold voltage. The author has an hindex of 31, co-authored 103 publications receiving 3396 citations. Previous affiliations of Mamidala Jagadesh Kumar include Indraprastha Institute of Information Technology & Indian Institutes of Technology.
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Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review
TL;DR: In this paper, the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications is examined.
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Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor
TL;DR: In this paper, a dual material gate (DMG) was applied to a tunnel field effect transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage.
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Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs
TL;DR: In this article, a 2D analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs).
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A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation
TL;DR: In this article, the authors presented the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET.
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Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device
TL;DR: In this article, a novel approach for forming a lateral bipolar chargeplasma transistor (BCPT) is explored using 2-D simulations, where different metal work function electrodes are used to induce n- and p-type charge-plasma layers on undoped silicon-on-insulator (SOI) to form the emitter, base, and collector regions of a lateral n-p-n transistor.