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Journal ArticleDOI

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

TLDR
In this article, a 2D analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs).
Abstract
A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.

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Citations
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Journal ArticleDOI

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

TL;DR: In this paper, the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications is examined.
Journal ArticleDOI

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

TL;DR: In this article, the authors presented the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET.
Posted Content

A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET - Two-dimensional Analytical Modeling and Simulation

TL;DR: In this paper, the authors presented the unique features exhibited by modified asymmetrical double gate (DG) silicon on insulator (SOI) MOSFET, which exhibits significantly reduced short channel effects.
Journal ArticleDOI

Effect of gate engineering in double-gate MOSFETs for analog/RF applications

TL;DR: It is demonstrated that TM-DG MOSFET can be a viable option to enhance the performance of SOI technology for high-frequency analog applications.
Journal ArticleDOI

A Junctionless Nanowire Transistor With a Dual-Material Gate

TL;DR: In this paper, a dual-material-gate junctionless nanowire transistor (DMG-JNT) was proposed and compared with a generic single-material gate JNT using 3D numerical simulations.
References
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Journal ArticleDOI

Short-channel effect in fully depleted SOI MOSFETs

TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Journal ArticleDOI

Dual-material gate (DMG) field effect transistor

TL;DR: In this paper, the dual material gate (DMG) FET was proposed and demonstrated, where the gate consists of two laterally contacting materials with different work functions, such that the threshold voltage near the source is more positive than that near the drain, resulting in a more rapid acceleration of charge carriers in the channel.
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A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology

TL;DR: In this paper, a novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated, and it is shown that by adding a layer of material with a larger work function to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability.
Journal ArticleDOI

Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering

TL;DR: In this article, two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology and two-dimensional (2D) numerical simulations reveal that the hetero-material gate field effect transistor (HMGFET) demonstrates extended threshold voltage roll-off to much smaller length and shows simultaneous transconductance enhancement and suppression of short-channel effects.
Journal ArticleDOI

Experimental 0.25-/spl mu/m-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique

TL;DR: In this article, the authors describe the fabrication process of quarter-micrometer-gate fully depleted CMOS/SIMOX devices, which is characterized by a new lateral isolation technique that can easily achieve 30nm-class surface planarization and 0.2-/spl mu/m-class isolation with no degradation of device characteristics.
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