There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The organization of behavior: A neuropsychological theory

The Personal Interview

What is modal logic

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Satisfiability (SAT) problem in engineering and computer science is to find the set of assignment values of input variables for the given Boolean function that evaluate this function to TRUE or prove that such satisfying values do not exist. For POS SAT Problem, we propose a novel quantum algorithm for the maximum satisfiability (MAX-SAT) which returns the maximum number of OR terms that are satisfied for the SAT-unsatisfiable function, providing us with the information how far the given Boolean function is from the SAT satisfaction. We use Grover's algorithm with a new block called quantum counter in the oracle circuit.

Quantum Algorithm for Maximum Satisfiability

We realize Surface Code quantum memories for nearest-neighbor qubits with always-on Ising interactions. This is done by utilizing multi-qubit gates that mimic the functionality of several gates. The previously proposed Surface Code memories rely on error syndrome detection circuits based on CNOT gates. In a two-dimensional planar architecture, to realize a two-qubit CNOT gate in the presence of couplings to other neighboring qubits, the interaction of the target qubit with its three other neighbors must cancel out. Here we present a new error syndrome detection circuit utilizing multi-qubit parity gates. In addition to speed up in the error correction cycles, in our approach, the depth of the error syndrome detection circuit does not grow by increasing the number of qubits in the logical qubit layout. We analytically design the system parameters to realize new five-qubit gates suitable for error syndrome detection in nearest-neighbor two-dimensional array of qubits. The five-qubit gates are designed such that the middle qubit is the target qubit and all four coupled neighbors are the control qubits. In our scheme, only one control parameter of the target qubits must be adjusted to realize controlled-unitary operations. The gate operations are confirmed with a fidelity of >99.9% in a simulated system consists of nine nearest-neighbor qubits.

Realization of Surface Code Quantum Memory on Systems with Always-On Interactions

This paper presents a methodology for logic synthesis of Boolean functions in the form of regular structures that can be mapped into standard cells or programmable devices. Regularity offers an elegant solution to hard problems arising in layout and test generation, at no extra cost or at the cost of increasing the number of gates, which does not always translate into the increase of circuit area. Previous attempts to synthesize logic into regular structures using decision diagrams suffered from an increase in the number of logic levels due to multiple repetitions of control variables. This paper proposes new techniques, which lead to fewer variable repetitions and significantly improve the performance of synthesis algorithms. Experimental results show that the generated regular circuits are larger in the number of gates and comparable in delay to the circuits without regularity produced by SIS, yet they exhibit a number of important advantages, such as localization and predictability of interconnect, reduction in the gate output load, and improved testability.

/pdf/logic-synthesis-for-layout-regularity-using-decision-3plei2h8kn.pdf

Logic Synthesis for Layout Regularity using Decision Diagrams

A generalization to the classical state minimization of a Finite State Machine (FSM) is described. The FSM is minimized here in two dimensions: numbers of both input symbols and internal states are minimized in an iterative sequence of input minimization and state minimization procedures. For each machine in the sequence of FSMs created by the algorithm an equivalent FSM is found that attempts 20 minimize the state assignment by selecting in each cell of the transition map one successor state from the set of successors. This approach leads to a partitioned realiration of the FSM with an input encoder. Our efficient branch-and-bound program, FMINI, produces an exact minimum result for each component minimization process and a globally quasi-minimum solution to the entire two-dimensional (2D) FSM combined process of state minimization and assignment.

/pdf/concurrent-two-dimensional-state-minimization-and-state-1j9okyuahe.pdf

Concurrent Two-Dimensional State Minimization and State Assignment of finite State Machines

Current processes validation methods rely on di- verse input states and exponential applications of state tomog- raphy. Through generalization of classical test theory exceptions to this rule are found. Instead of expanding a complete operator basis to validate a process, the objective is to utilize quan tum effects making each gate realized in the process act on a complete set of characteristic states and next extract functional in forma- tion. Random noise, systematic errors, initialization inaccuracies and measurement faults must also be detected. This concept is applied to the switching class comprising the search oracle. In a first approach, the test set cardinality is held constant to six; both testability and added depth complexity of an additional "design-for-test" circuit are related to the function real ized in the oracle. Oracles realizing affine functions are shown to gene rate no net entanglement and are thus the easiest to test, where oracles realizing bent functions are the most difficult to te st. A second approach replaces extraction complexity with a linear growth in experiment count. An interesting corollary of this study is the success found when addressing the classical test problem quantum mechanically. The validation of all classical degrees of freedom in a quantum switching network were found to necessitate exponentially fewer averaged observables than the number of tests in the classical lower bound.

/pdf/a-quantum-test-algorithm-tubcfhyz91.pdf

Marek Perkowski

Papers

Quantum Algorithm for Maximum Satisfiability

Realization of Surface Code Quantum Memory on Systems with Always-On Interactions

Logic Synthesis for Layout Regularity using Decision Diagrams

Concurrent Two-Dimensional State Minimization and State Assignment of finite State Machines

A Quantum Test Algorithm