There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The organization of behavior: A neuropsychological theory

The Personal Interview

What is modal logic

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

/pdf/multi-level-programmable-arrays-for-sub-micron-technology-3rk65sosap.pdf

Multi-Level Programmable Arrays for Sub-Micron Technology Based on Symmetries

This paper describes a CMOS-memristive programmable logic device connected to CMOS XOR gates (mPLD-XOR) for realizing multioutput functions well suited for two-level {NAND, AND, NOR, OR}-XOR-based design. This structure is a generalized form of AND–XOR logic where any combination of NAND, AND, NOR, and OR, and literals can replace the and level. For mPLD-XOR, the computational delay, which is measured as the number of clock cycles, equals the maximum number of inputs to any output XOR gate of a function assuming that the number of XOR gates is large enough to calculate the outputs of the function simultaneously. The input levels of functions are implemented with novel programmable diode gates, which rely on the diode-like behavior of self-rectifying memristors, and the output levels of functions are realized with CMOS modulo-two counters. As an example, the circuit implementation of a 3-bit adder and a 3-bit multiplier are presented. The size and performance of the implemented circuits are estimated and compared with those of the equivalent circuits realized with stateful logic gates. Adding a feedback circuit to the mPLD-XOR allows the implementation of a multilevel XOR logic network with any combination of sums, products, XORs, and literals at the input of any XOR gate. The mPLD-XOR with feedback can reduce the size and number of computational steps (clock cycles) in realizing logic functions, which makes it well suited for use in communication and parallel computing systems where fast arithmetic operations are demanding.

/pdf/a-time-efficient-cmos-memristive-programmable-circuit-qp8srrhe6j.pdf

A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND–XOR Structures

Encoding in Curtis-style decompositions is the process of assigning codes to g1'OUpS of compatible columns (or cubes) so that the binary logic descriptions of the predecessor (md successor sub-functions can be creatl::d for further decomposition. In doing so, the sub-functions created are functionally equivalent to the set of care values specified in the original fUTlction. In this paper an input/output encoding olgorithm DC.-ENC i.~ presented that is designed to achieve the simpliest total complexity of the predece.~sor and succe.~S01· sub-functions, and 10 increase the total numbel' of don't cares fOl' their further utilization in subsequent decomposition steps of these sub-functions.

/pdf/an-efficient-and-effective-approach-to-column-based-input-1yysv1d5mz.pdf

An efficient and effective approach to column-based input/output encoding in functional decomposition

This paper presents a synthesis algorithm, Covering Set Partitions (CSP), for reversible binary functions with no ancillary (garbage) bits. Existing algorithms are constrained to functions of small number of variables because they store the entire truth table of 2n terms in memory or require a huge amount of time to yield results because they must calculate all possible permutations of an input vector. In contrast, the CSP algorithm harnesses the natural mathematical properties of binary numbers, partially ordered sets and covering graph theory, to construct input vectors which are guaranteed to produce valid results. A randomly selected subset of all valid input vectors are processed where the best input vector sequence wins. The CSP algorithm is capable of synthesizing functions of large number of variables (30 bits) in a reasonable amount of time.

Reversible Function Synthesis of Large Reversible Functions with No Ancillary Bits Using Covering Set Partitions

A method is presented for describing parallel program graphs in a high-level synthesis system. Such descriptions are, in general, similar to Karp and Miller parallel program schemata and are more general than Petri nets. It is shown how these graphs are converted to sequential program schemata and then to finite state machines (FSMs) in such a way that the number of states is minimized. The entire FSM synthesizer for control unit synthesis in a comprehensive design automation system is presented and illustrated with a complete example. The synthesizer makes use of inputs and state minimization, state assignment, and logic minimization of FSMs. >

http://ieeexplore.ieee.org/iel5/143/3356/00112320.pdf

Marek Perkowski

Papers

Multi-Level Programmable Arrays for Sub-Micron Technology Based on Symmetries

A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND–XOR Structures

An efficient and effective approach to column-based input/output encoding in functional decomposition

Reversible Function Synthesis of Large Reversible Functions with No Ancillary Bits Using Covering Set Partitions

Generation of finite state machines from parallel program graphs in DIADES