M
Marek Perkowski
Researcher at Portland State University
Publications - 338
Citations - 6047
Marek Perkowski is an academic researcher from Portland State University. The author has contributed to research in topics: Logic synthesis & Boolean function. The author has an hindex of 38, co-authored 328 publications receiving 5809 citations. Previous affiliations of Marek Perkowski include East West University & Warsaw University of Technology.
Papers
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Journal ArticleDOI
One more way to calculate generalized Reed-Muller expansions of boolean functions
B.J. Falkowski,Marek Perkowski +1 more
TL;DR: A new algorithm is given that converts disjoint cube representation of boolean functions into fixed-polarity generalized Reed-Muller expansions (GRME) and is much more efficient than the fast algorithm.
Proceedings ArticleDOI
Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations
TL;DR: The present paper presents a new representation of multiple-valued relations (functions in particular), calledmultiple-valued cube diagram bundles (MVCDB), which improves on rough partition representation by labeling their blocks with variable values and by representing blocks efficiently.
Book ChapterDOI
Minimization of permuted Reed-Muller Trees for cellular logic programmable Gate arrays
Li-Fei Wu,Marek Perkowski +1 more
TL;DR: In this paper, the authors present two programs, exact and approximate, for the minimization of Permuted Reed-Muller Trees that are obtained by repetitive application of Davio expansions (Shannon expansions for EXOR gates) in all possible orders of variables in subtrees.
Journal ArticleDOI
Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions
TL;DR: This paper introduces several new families of decision diagrams for multi-output Boolean functions, including Kronecker Decision Diagrams (KDDs) with negated edges, which can provide a more compact representation of functions than either of the two decision diagrams.
Proceedings ArticleDOI
Ternary and quaternary lattice diagrams for linearly-independent logic, multiple-valued logic, and analog synthesis
TL;DR: Ternary and quaternary lattice diagrams are introduced that can find applications to submicron design, and designing new fine-grain digital, analog and mixed FPGAs.