There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The organization of behavior: A neuropsychological theory

The Personal Interview

What is modal logic

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

This paper presents a heuristic cost minimization approach to synthesizing linear reversible circuits. Two bidirectional linear reversible circuit synthesis methods are introduced, the Alternating Elimination with Cost Minimization method (AECM) and the Multiple CNOT Gate method (MCG). Algorithms, example syntheses, and extensions to these methods are presented. An MCG variant which incorporates line reordering is introduced. Tests comparing the new cost minimization methods with the best known method for large circuits are presented. Results show that of the three methods MCG had the lowest average CNOT gate counts for linear reversible circuits up to 24 lines, and that AECM had the lowest counts between 28 and 60 lines.

/pdf/a-cost-minimization-approach-to-synthesis-of-linear-46cy7a52tb.pdf

A Cost Minimization Approach to Synthesis of Linear Reversible Circuits.

In this paper we introduce a set of resources used to describe multiple-valued (MV) functions: a set of multiple-valued benchmarks and a file format specifically designed to accommodate the requirements of multiple-valued function representation. The proposed functions are intended for use as reference benchmarks for automated synthesis algorithms of multiple-valued circuits. In the MV domain, functions can be represented using fixed radices (e.g. ternary, quaternary, etc) or using mixed radices (hybrid functions). Since such functions are harder to represent with the existing PLA specification, in this paper, we introduce the eXtensible Quantum Specification (XQS) file format which is based on the well-known YAML file specification.

Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format

We present the results of application of Evolutionary Algorithms to the problem of synthesizing quantum circuits which belong to the class of reversible circuits, represented as an input/output mapping vectors. The paper specifically focuses on large quantum circuits where many valid solutions exist in an exponentially inflating search space. Valid solutions represent the set of all input vector permutations (arrangements) which satisfy the circuit specification. The search space for circuits with large number of variables grows exponentially making it impossible to discover the set of optimal solutions. The paper compares three methods for selecting valid solutions of input vector sequences: 1) randomly, 2) genetic algorithm, 3) Tabu search. The objective function calculates the number of elementary quantum gates needed to represent the solution such that lower number of gates represents better solutions. In addition to the choice of selection algorithm, we illustrate the impact of using different partition depths for the Covered Set Partitions algorithm used to construct valid input vector sequences.

/pdf/application-of-genetic-algorithm-for-synthesis-of-large-28huh1arf2.pdf

Application of Genetic Algorithm for Synthesis of Large Reversible Circuits using Covered Set Partitions

A compact data representation, in which the typically required operations are performed rapidly, and effective and efficient algorithms that work on these representations are the essential elements of a successful CAD tool. The objective of this paper is to present a new data representation—term trees (TTs)—and to discuss its application for an effective and efficient structural automatic test-pattern generation (ATPG). Term trees are decision diagrams similar to BDDs that are particularly suitable for structure representation of AND–OR and AND–EXOR circuits. In the paper, a flexible algorithm for minimum term-tree construction is discussed and an effective and efficient algorithm for ATPG for AND–EXOR and AND–OR circuits is proposed.

/pdf/term-trees-in-application-to-an-effective-and-efficient-atpg-55559que4m.pdf

Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits

We introduce a novel volistor logic gate which uses voltage as input and resistance as output. Volistors rely on the diode-like behavior of rectifying memristors. We show how to realize the first logic level, counted from the input, of any Boolean function with volistor gates in a memristive crossbar network. Unlike stateful logic, there is no need to store the inputs as resistances, and computation is performed directly. The fan-in and fan-out of volistor gates are large and different from traditional memristor circuits. Compared to solely memristive stateful logic, a combination of volistors and stateful inhibition gates can significantly reduce the number of operations required to calculate arbitrary multi-output Boolean functions. The power consumption of volistor logic is computed and compared with the power consumption of stateful logic using the simulation results obtained by LTspice—when implemented in a 1 × 8 or an 8 × 1 crosspoint array, volistors consume significantly less power.

/pdf/memristor-based-volistor-gates-compute-logic-with-low-power-2x7pj9pgw1.pdf

Marek Perkowski

Papers

A Cost Minimization Approach to Synthesis of Linear Reversible Circuits.

Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format

Application of Genetic Algorithm for Synthesis of Large Reversible Circuits using Covered Set Partitions

Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits

Memristor-Based Volistor Gates Compute Logic with Low Power Consumption