Journal ArticleDOI
Modeling Advanced FET Technology in a Compact Model
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TLDR
In this paper, a holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET.Abstract:
The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-large-scale-integration circuit applications of new technologies. This paper presents some of the efforts toward the modeling of new technologies for bulk MOSFETs and multigate transistors. A holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET. A new analytical model is also presented for the fundamentally new device structure-FinFETread more
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FinFETs and Other Multi-Gate Transistors
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution
TL;DR: New techniques for logic circuits and interconnect, for memory, and for clock and power distribution are discussed, and the role of geometrically regular circuits as one promising solution is discussed.
Journal ArticleDOI
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS
TL;DR: In this article, the authors present a survey of recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.
Journal ArticleDOI
BSIM—SPICE Models Enable FinFET and UTB IC Designs
Navid Paydavosi,Sriramkumar Venugopalan,Yogesh Singh Chauhan,Juan Pablo Duarte,Srivatsava Jandhyala,Ali M. Niknejad,Chenming Calvin Hu +6 more
TL;DR: Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs and they are selected as the world's first industry-standard compact model for the FinFET.
Journal ArticleDOI
A Review on Compact Modeling of Multiple-Gate MOSFETs
TL;DR: This paper reviews recent development on compact modeling of multiple-gate (MG) MOSFETs and finds that by adding quantum mechanical effects and short-channel effects, the core model has been expanded into a full-blown compact model which has been calibrated to and validated by experimental FinFET hardware.
References
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Journal ArticleDOI
Piezoresistance Effect in Germanium and Silicon
TL;DR: In this article, the complete tensor piezoresistance has been determined experimentally for these materials and expressed in terms of the pressure coefficient of resistivity and two simple shear coefficients.
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Journal ArticleDOI
CMOS scaling into the nanometer regime
Yuan Taur,Douglas A. Buchanan,Wei Chen,David J. Frank,Khalid EzzEldin Ismail,Shih-Hsien Lo,George Anthony Sai-Halasz,R. Viswanathan,Hsing-Jen Wann,Shalom J. Wind,Hon-Sum Philip Wong +10 more
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Proceedings ArticleDOI
FinFET scaling to 10 nm gate length
Bin Yu,Leland Chang,Shibly S. Ahmed,Haihong Wang,Scott A. Bell,Chih-Yuh Yang,Cyrus E. Tabery,Chau M. Ho,Qi Xiang,Tsu-Jae King,Jeffrey Bokor,Chenming Hu,Ming-Ren Lin,D. Kyser +13 more
TL;DR: In this paper, the authors report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm.