Om Prakash

TL;DR: Results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability.

TL;DR: It is shown that poorer electrostatics in a FeFET due to a thicker oxide does not degrade the overall variation when comparing to a baseline FinFET and a thin oxide reference transistor, and ferroelectric parameters uniformity should also be one of the primary optimization targets towards building reliable FeFet-based non-volatile memory.

TL;DR: The read voltage of FeFET based nonvolatile memory (NVM) can be carefully selected to mitigate deleterious effects of temperature variation during runtime.

TL;DR: In this paper, the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor (NC-nFinFET) was investigated using TCAD models, which are well calibrated against 14nm production quality FinFETs.

TL;DR: In this article, a well-calibrated predictive and scalable compact Verilog-A-based model, integrated with an NBTI model for sub-20nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, is presented.