Showing papers in "IEEE Transactions on Device and Materials Reliability in 2017"

Failure and Reliability Analysis of a SiC Power Module Based on Stress Comparison to a Si Device

Abstract: The superior electro-thermal properties of silicon carbide (SiC) power devices permit higher temperature of operation and enable higher power density compared with silicon devices. Nevertheless, the reliability of SiC power modules has been identified as a major area of uncertainty in applications which require high reliability. Traditional power module packaging methods developed for silicon chips have been adopted for SiC and the different thermomechanical properties cause different fatigue stresses on the solder layer of the chip. In this paper, a 2-D finite element model has been developed to evaluate the stress performance and lifetime of the solder layer for Si devices, which has been validated using accelerated power cycling tests on Si IGBTs. The proposed model was extrapolated for SiC devices of the same voltage and current rating using the same solder material and the results show that under the same cyclic power loss profile the induced stress and strain energy in the die attach layer is much higher and concentrates on the die/solder interfacial area for SiC chips. Using the validated stress-based model, the lifetime can be quantified when SiC chips are used. This ability to extrapolate the available power cycling and lifetime data of silicon chips to SiC chips would be a key element for developing reliable packaging methods for SiC devices.

Design and Evaluation of an Efficient Schmitt Trigger-Based Hardened Latch in CNTFET Technology

Abstract: This paper presents a Schmitt trigger (ST) buffer using carbon nanotube FET (CNTFET) for reliable low-power applications. Nanoscale circuits are more susceptible to transient faults or soft errors due to the reduction of the stored charge in their sensitive nodes. Hereupon, low-cost and tolerant circuits design is a significant challenge, especially in the nanoscale storage cells. In addition, the proposed ST is utilized for designing a low-power hardened latch. In the proposed design, instead of up-sizing and increasing the input capacitance, the determined hysteresis mechanism of the proposed ST buffer is utilized to improve the single event upset hardness. The simulations are conducted based on the Stanford CNTFET model at 16-nm technology node. According to the results, the proposed ST has on average 90% lower power-delay product and higher robustness to PVT variations as compared to its most efficient CNTFET-based counterparts. Moreover, the simulations confirm the considerable tolerance of the proposed hardened latch to the multiple node upset as compared to the state-of-the-art designs. The proposed hardened latch has on average 68% higher critical charge, which considerably enhances its reliability and on average 16% smaller area as compared to its counterparts.

Online Calculation of the Increase in Thermal Resistance Caused by Solder Fatigue for IGBT Modules

Abstract: This paper addresses the catastrophic failure of power converter systems caused by the aging of the insulated-gate bipolar transistor (IGBT) module. Monitoring the aging state of IGBT in real time enables the defective module to be found and be replaced timely. Solder fatigue increasing the internal thermal resistance of the module has been identified as one of the main root causes of IGBT module aging. In this paper, a novel event-driven solder fatigue monitoring mechanism is proposed. The proposed method consists of two models which are a dynamic solder aging monitoring model and an event-driven online calculation model of the increase in thermal resistance. The dynamic solder aging monitoring model detects solder fatigue in real time by the variations of case temperatures with thermal sensors on the bottom surface of the baseplate. The event-driven online calculation model estimates the increase in thermal resistance at the occurrence of the solder aging event by the junction temperature from thermosensitive electrical parameters, which are not affected by the solder fatigue. With the cooperation of two models, the aging level of the IGBT module caused by solder fatigue is evaluated. Simulation and experimental results are provided to verify the effectiveness of the proposed method.

Soft Errors Induced by High-Energy Electrons

Abstract: In the semiconductor reliability community, soft error research has primarily focused on neutrons and alpha particles. However, there are certain situations and environments in which high-energy electrons may also lead to soft errors. In this paper, we show that high energy electrons and the secondary particles created by them are capable of producing soft errors. In this paper, the energy dependence of electron-induced soft errors in a 28 nm bulk CMOS SRAM-based FPGA is recorded. Error rates are measured in both the embedded RAM and configuration RAM of the FPGA. This paper is the first research to explore the energy dependence of electron-induced single-event upsets in a commercial-off-the-shelf device. The measured electron-induced error cross sections are between $10^{{-20}}$ and $10^{{-17}}~ {\rm cm}^{{2}}$ /bit depending on memory cell tested and the electron energy. Monte Carlo energy deposition simulations are used to further explore the mechanisms involved.

Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric

Abstract: In this paper, we investigate for the first time effect of positive (donor) and negative (acceptor) interface trap charges on the performance of proposed heterogeneous gate dielectric (HD) electrically doped tunnel field-effect transistor (EDTFET) in terms of dc, analog/RF, and linearity distortion parameters, where the HD layer is considered as a gate dielectric to improve the ON-state current and device performance. For this, a comparative analysis has been performed between conventional and proposed EDTFET with identical dimensions in the presence of interface trap charges. ATLAS device simulation of both devices is performed for different performance metrics such as transfer characteristics, parasitic capacitances, device efficiency, output conductance ( $\text{g}_{ {ds}}$ ), cut-off frequency ( $\text{f}_{ {t}}$ ), and gain bandwidth product. However, linearity distortion parameters of the proposed device such as third-order transconductance coefficient ( $\text{g}_{ {m3}}$ ), VIP2, VIP3, IIP3, and IMD3 are also investigated. The device simulations show that HD-EDTFET is more immune in terms of performance variation than conventional EDTFET with different interface trap charges available at the Si/SiO2 interface. Thus, it can be utilized as a suitable candidate for low power analog/RF applications.

Selectivity Tuning of Graphene Oxide Based Reliable Gas Sensor Devices by Tailoring the Oxygen Functional Groups: A DFT Study Based Approach

Abstract: This paper concerns the selectivity tuning of graphene oxide based gas sensor devices, where the role of oxygen functional groups like, carboxyl, carbonyl, hydroxyl (sp2), epoxy, and hydroxyl (sp3) were investigated for physisorption of NO2, NH3, CO, and H2O using first principle calculation (density functional theory) incorporating Atomistix Toolkit (v2015.1). Among the five functional groups under consideration, carboxyl, carbonyl, and hydroxyl (sp2) were considered at the edges on the basal plane, while epoxy and hydroxyl (sp3) groups were considered in the plane perpendicular to that. For all the species, the optimum positions for adsorption, adsorption energy and charge transfer efficiency were investigated for the above two planes. It was found that edge carboxyl group is the most favorable in terms of adsorption energy and charge transfer efficiency targeting NH3, CO, and H2O. On the contrary, for NO2, hydroxyl functionalization was found to be the most efficient one.

Charge Trapping Analysis of Metal/Al 2 O 3 /SiO 2 /Si, Gate Stack for Emerging Embedded Memories

Abstract: For Al2O3 charge trapping analysis, Metal/Al2O3/SiO2/Si (MAOS) structures are fabricated from atomic layer deposition and plasma enhanced chemical vapor deposition-based Al2O3 and SiO2 thin films, respectively. The fabricated MAOS devices showed high memory window of ~7.81V@16V sweep voltage and leakage current density of ${\sim } 3.88{\times }10^{{-6}}\text{A}$ /cm $^{{2}}$ @−1V. The charge trapping and decay mechanism are investigated with the variation of alumina thickness by Kelvin probe force microscopy (KPFM). It reveals that vertical charge decay is a dominant phenomenon of charge loss for Al2O3 in contrast to lateral charge spreading. Constant current stress (CCS) measurements mark the location of charge trap centroid at ~10.30 nm from metal/Al2O3 interface attributes that bulk traps present close to the Al2O3/SiO2 interface are dominant charge trap centres. In addition, a simple method is proposed to estimate the trap density using KPFM and CCS method at room temperature. Furthermore, there is ~28% exponential decay in high state capacitance observed after $10^{{4}}$ s in capacitance-time analysis at room temperature. This material engineering of charge traps will improve the performance and functionality of bilayer Al2O3/SiO2 structure for embedded memory applications.

Non-Uniform Aged Modules Reconfiguration for Large-Scale PV Array

Abstract: In the past decades, a large number of photovoltaic (PV) plants have been built. Due to the minor physical differences between PV cells and the influence of environmental factors such as rains, temperature, and humidity, the aging of a PV array is often distributed unevenly within each PV module. This non-uniform aging causes further decreased output power, which is often easily observed for large size PV arrays. Although the global maximum power point tracking (GMPPT) strategy can improve the output power, the GMPPT cannot exploit the maximal power generation potential from non-uniform aging PV arrays. In order to exploit further the power generation potential and extend the service time of non-uniform aging PV arrays, a novel PV array reconfiguration method is developed in this paper. The concept of cell unit is applied to investigate the aging phenomenon of PV modules, and each PV module is assumed to be composed of three submodules, while these three submodules within any single PV module might have different aging conditions and, thus, different power-output capacities. The challenge is how to rearrange the PV array under the cases where: 1) each PV module has non-uniformly aged cell units; 2) there are a large number of PV modules; and 3) the voltage working range is restricted. To solve these problems, a nonlinear integer programming problem is formulated to maximize the power output under the constraints of non-uniformly aging and voltage restrictions. A small size $7\times10$ PV array is simulated to illustrate the proposed method. Furthermore, medium size $20\times 10$ and large size $125\times20$ PV arrays are employed to verify the feasibility of the proposed method. A 1.5 kW $2\times 4$ real PV array under non-uniform aging conditions is presented and experimentally tested to confirm the proposed rearrangement method.

Analytical Modeling of Electromigration Failure for VLSI Interconnect Tree Considering Temperature and Segment Length Effects

Abstract: Electromigration (EM) is a major concern for very large-scale integration (VLSI) interconnect reliability, particularly for interconnect trees with multibranch metal wires representing continuously connected metal (Cu) lines terminated at diffusion barriers. For EM modeling and assessment, one important problem is to perform fast EM time to failure analysis for practical VLSI chips. Compact modeling for EM effects for the interconnect tree has been studied recently to better EM signoff analysis. But the existing method cannot consider wires stressed under time-varying temperature, which is very typical for practical chip working conditions. In this paper, we develop the exact analytic model for the stress evolution of interconnect trees under different current density and varying segment length from the first principle. Due to the difficulty in obtaining the exact analytical solution, we focus on three-terminal wire in this paper. The stress evolution is modeled by two Korhonen’s equations coupled through boundary conditions which are solved with the Laplace transformation technique. The new analytical EM model is further extended to consider the time-varying temperature stressing condition and initial non-zero residual stress. The proposed method is compared with the finite-element method (FEM) tool COMSOL, the recently proposed eigenfunction-based method, and the published EM simulator XSim. The comparison shows that the analytical solution agrees well with the results from the FEM numerical analysis. It uses much fewer terms compared to the eigenfunction method for the same accuracy. It also agrees very well with XSim, which is consistent with the previously reported measured results.

A 2.5 GHz Low Power, High- ${Q}$ , Reliable Design of Active Bandpass Filter

Abstract: In this paper, a variation-aware and reliable design of a fully integrated radio frequency (RF) bandpass filter realized using a voltage differencing transconductance amplifier is presented. The filter is characterized by its high frequency operation, low power consumption, high quality factor, and it is insensitive to process, voltage, and temperature variations. Sensitivity analysis has been performed to analyze the circuit performance in the presence of parasitics. The inductor-less approach finds its application in integrated building blocks of RF front ends, thus eliminating the requirement of off-chip filters in transceivers. Centered at 2.511 GHz and operating within the 36.21 MHz 3-dB bandwidth, the filter draws 0.168 mA from a ±1 V power supply, attains a voltage gain of 72.6 dB, a quality factor of 69.34 and noise figure of ~29.6 dB. In addition, it has a dynamic range of 125.84 dB-Hz and a 1-dB compression of −1.5 dBm which translates into a figure of merit as high as 94 dB.

Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design

Abstract: Very large-scale integrated circuit design, based on today’s CMOS technologies, are facing various challenges. Shrinking transistor dimensions, reduction in threshold voltage, and lowering power supply voltage, cause new concerns such as high leakage current, and increase in radiation sensitivity. As a solution for such design challenges, hybrid MTJ/CMOS based design can resolve the issue of leakage power and bring the advantage of nonvolatility. However, radiation-induced soft error is still an issue in such new designs as they need peripheral CMOS components. As a result, these magnetic-based circuits are still susceptive to radiation effects. This paper proposes a radiation hardened and low power magnetic full-adder (MFA) for advanced microprocessors. Comparing with the previous work, the proposed MFA is capable of tolerating any particle strike regardless of the induced charge. Besides, our MFA circuit offers a lower energy consumption in write operation as compared with previous counterparts. We also suggest an incremental modification to the proposed MFA circuit to give it the advantage of full nonvolatility for future nonvolatile microprocessors.

Characterizing Interfacial Sliding of Through-Silicon-Via by Nano-Indentation

Abstract: In this paper, an experimental method is proposed to determine the shear sliding behavior of the interface between a copper through-silicon-via (TSV) and silicon. This interface was loaded in a nano-indentation experiment on specimens that were fabricated using focused-ion-beam milling. The elastic and plastic properties of the copper via were first characterized by micro-pillar compression experiments. The interfacial sliding is described by a cohesive zone model with a traction-separation relation including a linearly elastic part followed by frictional sliding at a constant shear traction. Both analytical and numerical models were developed for extracting the parameters of the traction-separation relation for the shear behavior of the interface. The average critical shear traction required to initiate interfacial sliding was found to be 77.2 MPa and the corresponding relative displacement across the interface was 182.7 nm, while the frictional shear strength was 25 MPa. The traction-separation relation with the extracted parameters may be used to study via extrusion and associated reliability analysis for integrated TSV structures.

Soft-Failures Induced by System-Level ESD

Abstract: Hundreds of static discharges were directed to a circuit board containing a custom test chip, and the resulting soft-failures were recorded. The large time-derivative of the ESD current is the primary cause of soft-failures in this system. Magnetic coupling between traces and bondwires produces glitches at IO pins; the magnitude of these glitches is increased by the bounce of the on-chip supply net relative to the on-board supply. Additionally, logic upsets due to substrate current collection are observed when the equipment-under-test is tethered, i.e., when it has a low impedance path to Earth-ground.

Experimental Investigation of NBTI Degradation in Power VDMOS Transistors Under Low Magnetic Field

Abstract: In this paper, we report an experimental evidence of the impact of applied a low magnetic field ( ${B ) during negative bias temperature instability (NBTI) stress and recovery, on commercial power double diffused MOS transistor. We show that both interface ( ${\Delta }{N_{it}}$ ) and oxide trap ( ${\Delta }{N_{ot}}$ ) induced by NBTI stress are reduced by applying the magnetic field. This reducing is more pronounced as the magnetic field is high. However, the dynamic of interface trap during stress and recovery phase is not affected by the applied magnetic field. While, the dynamic of oxide trap is affected in both stress and recovery phases.

Impact of X-Ray Tomography on the Reliability of Integrated Circuits

Abstract: X-ray tomography provides 3-D information of an integrated circuit (IC) and has been utilized for counterfeit detection. Although it is a nondestructive process, electrical functionalities of IC under long time radiation has yet to be fully investigated. This paper analyzes the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3-D imaging on Intel flash memories, Macronix flash memories, Xilinx Spartan 3, and Spartan 6 FPGAs and test the electrical functionalities after each round of tomography. We examine the impact of tomography on erase time, read margin, and program operation in flash memories. The change of ring oscillators frequency mapped in FPGAs is also investigated. A major finding is that tomography increases the erase time of flash memory of older technology nodes, eventually resulting in failure. In contrast, the flash and Xilinx FPGAs of newer technologies seem much less sensitive to tomography, as only minor degradations are observed. Degradation of IC performance is explained by considering total ionization dose effect due to tomography. Counterfeit detection requires approximately 2 h of tomography and no IC failed permanently during this time period.

A New SiC Trench MOSFET Structure With Protruded p-Base for Low Oxide Field and Enhanced Switching Performance

Abstract: The high OFF-state oxide field in the SiC trench MOSFET is a threat for its long term reliability, and thus hinders the wide acceptance of the SiC trench MOSFETs. In this paper, an SiC trench MOSFET with protruded p-bases (PB-MOS) is proposed, which features protruded p-bases to shield the gate oxide at the trench bottom against the high OFF-state drain voltage. Numerical device simulations based on Sentaurus TCAD verify the benefits of the structure. The OFF-state oxide field ( ${ {E}}_{\text {ox-m}}$ ) in the PB-MOS is 1.7 MV/cm, which is dramatically lower compared to the high ${ {E}}_{\text {ox-m}}$ of 8.6 MV/cm in the conventional trench MOSFET (C-MOS). The above benefit is achieved without sacrificing device performances. The reverse transfer capacitance ( ${ {C}}_{\text{rss}}$ ) of the PB-MOS is around ten times lower than that in the C-MOS. Both the gate charge ( ${ {Q}}_{\text{G}}$ ) and the gate-to-drain charge ( ${ {Q}}_{\text{GD}}$ ) of the PB-MOS are significantly improved compared to the C-MOS. A low specific ON-resistance ( ${ {R}}_{\text{ON}}$ ) is maintained in the PB-MOS by using additional JFET doping to compensate the JFET effect. As a result, the PB-MOS presents much better figures of merit ${ {Q}}_{\text{G}} \cdot { {R}}_{\text{ON}}$ and ${ {Q}}_{\text{GD}} \cdot { {R}}_{\text{ON}}$ than those of the C-MOS. The PB-MOS achieves a much faster switching speed than the C-MOS, and consequently exhibits an appreciable reduction in the switching energy loss.

Reliability-Aware Circuit Design Methodology for Beyond-5G Communication Systems

Abstract: This paper focuses on efficient reliability analysis methodologies applicable for beyond-5G communication systems demonstrated on prospective terahertz (THz) technologies Recently, a lot of the research interests have grown on optoelectronic integration which requires simultaneous management of electronic and optical modules These technologies are evolving very rapidly, providing higher complexity, thereby increasing their susceptibility to stress environments (ie, mutual self-heating) and finally requiring both robustness assessment and lifetime prediction under different operating conditions Consequently, long-time reliability is a major issue Extensive reliability assessment needs novel design methodologies that can provide reliability-aware optimization at the design level This review discusses an extensive physics-based methodology for reliability prediction and analysis of degradation mechanisms in integrated-circuit technologies Circuit-level design and optimization methodologies are illustrated by taking into account reliability-aware design techniques Application examples and results are presented for an InP DHBT process, a viable technological solution for beyond-5G and THz applications

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

Abstract: For sub-20-nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, negative bias temperature instability (NBTI) is an important reliability issue and requires an accurate model to predict device and circuit performance. In this paper, we report a well-calibrated predictive and scalable compact Verilog-A-based compact model, integrated with an NBTI model for NW CMOS circuit simulation and design. The stress and recovery NBTI model for an Si NW field-effect transistor is obtained from experimental NW pMOSFETs using a range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar metal-oxide semiconductor field-effect transistors. This is attributed to its cylindrical gate structure, resulting in enhanced 2-D hydrogen diffusion and stress-induced Si/SiO2 traps. This emphasizes the need to evaluate NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: an inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, the interface states generation, inverter delay, and RO frequency degrade rapidly and saturate over the long-term 10-year lifetime. Finally, the design of the SRAM cell employing the multiwire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using the appropriate design configuration. This paper underscores the need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at the device and circuit level.

A Nonvolatile, Low-Power, and Highly Reliable MRAM Block for Advanced Microarchitectures

Abstract: Following the scale down of complementary metal-oxide semiconductor (CMOS) technology, radiation-induced soft errors have become a concerning issue in CMOS circuit design. Today’s integrated circuits suffer from single event double node upset (SEDU) that takes place when an energetic particle strike affects two adjacent nodes. In this letter, a magnetic random access memory block capable of tolerating SEDUs is proposed and evaluated. The proposed circuit utilizes a hybrid design of magnetic and CMOS-based technology that considerably reduces the static power, improves the performance, and offers the advantage of nonvolatility. Simulation results validated that the proposed circuit is fully single event upset and also SEDU immune beside the other advantages offered.

Effect of Microstructure and Anisotropy of Copper on Reliability in Nanoscale Interconnects

Abstract: The mechanical behavior of copper is highly anisotropic. Although it is a face centered cubic crystal, the elastic constants vary considerably for different crystallographic orientations. Typically, the copper metal conductor lines in integrated circuits are polycrystalline in nature. In this paper, we utilize Voronoi tessellation to model the polycrystalline microstructure for the copper metal lines in test structures and then assign textured orientation to each grain and assign corresponding anisotropic elastic constants based on the assigned orientation. By subjecting the test structure through a thermal stress, we observe over 10x variation in normal stresses along the grain boundaries depending on the orientation, dimensions, surroundings, and location of the grains. This may introduce new weak points within the metal interconnects where normal stresses can be very high depending on the orientation of the grains leading to delamination and accumulation sites for vacancies. Hence, inclusion of microstructures and corresponding anisotropic properties for copper grains is critical to conduct a realistic study of both stress voiding and electromigration phenomena, especially at smaller nodes where the anisotropic effects are significant. Further, a comparison between stress levels in test structures with SiCOH and SiO2 as the inter level dielectric was conducted.

Statistical Distribution of Through-Silicon via Cu Pumping

Abstract: Cu pumping is defined as the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. In previous publications both a lognormal distribution and a distribution of the maximum of two normal variables were used to fit experimental data. In this paper, these two types of statistical distribution are compared, showing that the maximum of two normal distributions provides a better fit, in particular at the right tail which is more significant for the potential reliability impact of Cu pumping. Also, it is shown how Cu pumping is determined by the network of random high angle grain boundaries in the Cu region near the TSV top, as an extension of a previous analysis which occurred at the TSV top surface only. This relation between Cu pumping and Cu microstructure provides a physical interpretation of the maximum of two normal distributions, based on the deformation mechanisms underlying Cu pumping.

Mechanism of Depletion-Mode TDDB for 4H-SiC MOS Structure

Abstract: The depletion-mode time-dependent dielectric breakdown (DM-TDDB) mechanism was investigated with n-type 4H-SiC MOS capacitors depleted by high-voltage dc bias. Under the DM-TDDB stress, the hole generation beneath the oxide/SiC interface and its injection into the oxide appeared in the current measurement results. The lifetime distribution was clearly divided into two groups: shorter and longer time to breakdown ( ${t}_{\mathbf {BD}} $ ). The breakdown point for the shorter ${t}_{\mathbf {BD}} $ was located close to a threading dislocation (TD) of the 4H-SiC, whereas the capacitors for the longer ${t}_{\mathbf {BD}} $ contained no dislocation. For the longer ${t}_{\mathbf {BD}} $ , the charge-to-breakdown ( ${Q}_{\mathbf {BD}} $ ) decreased from approximately 4.5 to 0.1 C/cm $^{2}$ with an increase in the electric potential drop ( ${V}_{\mathbf {SiC}} $ ) below the interface at 503 K, demonstrating that the high-energy-hole injection lowers the lifetime. For the shorter ${t} _{\mathbf {BD}}$ , the TD was presumed to induce the additional hot-hole injection from the deeper depletion region into the local oxide and thereby precipitate the percolation path formation.

OPTIMAS: Overwrite Purging Through In-Execution Memory Address Snooping to Improve Lifetime of NVM-Based Scratchpad Memories

Abstract: SRAM-based scratchpad memories (SPMs) used in embedded systems impose high leakage power Designing SPMs based on non-volatile memories (NVMs) were proposed as NVMs have negligible leakage power The main problem of utilizing NVMs across the SPM is their limited number of write cycles (endurance) This problem threatens the reliability of NVM-based SPMs To alleviate the problem of limited endurance in NVM-based SPMs, this paper proposes a method, called overwrite purging through in-execution memory address snooping (OPTIMAS) The main idea behind the proposed method is to control the lifetime of NVM-based SPMs, directly by a hardware unit, outside of the SPM mapping algorithm This idea enables the possibility of using traditional SRAM-based mapping algorithms in NVM-based SPMs OPTIMAS controls the wear-out of NVM-based SPMs based on the recent write behavior of each block during the runtime of the programs OPTIMAS is evaluated from the lifetime, energy consumption, and performance point of views The simulation results show up to two orders of magnitude improvement in lifetime, an average of 50% reduction in dynamic energy consumption, and negligible performance overhead (less than 1%) Furthermore, it is shown that while OPTIMAS is orthogonal to all other approaches, it benefits from significant lifetime improvement in comparison with the state-of-the-art approaches

Improving MOSFETs’ TID Tolerance Through Diamond Layout Style

Abstract: This letter describes an experimental comparative study of the total ionizing dose (TID) effects due to Co-60 gamma irradiation between hexagonal (Diamond) and conventional rectangular gates metal-oxide semiconductor field-effect transistors (MOSFETs), regarding the same bias conditions during irradiation. The transistors were manufactured by using the 350 nm commercial bulk complementary metal-oxide semiconductor (CMOS) integrated-circuits (ICs) technology. The innovative hexagonal gate layout proposal can reduce the parameter deviations of TID effects in MOSFETs in, approximately, 30%, 400%, and 100% in terms of the threshold voltage, leakage drain current, and subthreshold slope, respectively, regarding the standard MOSFET counterparts. Therefore, the Diamond MOSFET can be considered as a low-cost alternative device to be used in space CMOS ICs applications.

Simulation Study of Large-Scale Charge Sharing Mitigation Using Seamless Guard Band

Abstract: In this paper, a novel seamless guard band (SGB) technique for charge sharing mitigation is studied using 3-D TCAD numerical simulations. The simulations results in 65-nm twin-well bulk CMOS technology indicate that the SGB technique can not only mitigate the single-event transient pulsewidth greatly but also mitigate the charge sharing between logical nodes or logical cells significantly. The simulation results also indicate that the SGB technique is superior to the conventional guard band (GB) technique, for it is more beneficial for parasitic bipolar effect mitigation. Using SGB technique, the single-event double-transient (SEDT) generation is mitigated completely under low LET particle (LET $\le \text{40}\ \text{MeV}\cdot \text{cm}^{2}/\text{mg}$ ) radiation, and the SEDT pulsewidth is mitigated > 50% even with the LET of 80 $\text{MeV}\cdot \text{cm}^{2}/\text{mg}$ , which is > 25% from GB technique. Finally, the SGB technique can be applied to the construction of a radiation-hardened standard cell library conveniently, and its area penalty is 1–1.67 $\times$ , which is the same with that of the GB technique.

Material Characterization and Low Cycle Fatigue Model of Low Ag Content Lead-Free Solder

Abstract: In this paper, a method of design-for-reliability for the advanced electronic package under temperature cycling (TC) condition is demonstrated, including material characterization, reliability test, finite element analysis (FEA), and fatigue life model development. Tensile tests are conducted for Sn–1.0Ag–0.5Cu–0.02Ni (SAC105Ni0.02) solder alloy at four stain rates of $10^{{-5}}$ , $10^{{-4}}$ , $10^{{-3}}$ , and $10^{{-2}}$ and four test temperatures of − 35°C, 25 °C, 75 °C, and 125 °C to develop temperature- and strain rate-dependent material models. Tensile creep tests are carried out at various temperatures and stress levels to study creep behavior. TC reliability test is conducted for ball grid array package with SAC105Ni0.02 solder joints. Thermal fatigue lives are obtained from TC test with different failure rates. FEA simulation is carried out for each package using the developed mechanical properties and creep model of the solder. Fatigue life models with different failure rates are proposed for the SAC105Ni0.02 solder by combining simulation results and experimental data. Fatigue resistance of the SAC105Ni0.02 solder is comparable with that of high Ag content SAC solders.

Lateral DMOS With Partial-Resist-Implanted Drift Region for Alleviating Hot-Carrier Effect

Abstract: Maximum operating gate voltage ( ${\mathbf{V}}_{\mathbf{gmax}} $ ) stress is observed and confirmed as the worst hot-carrier degradation condition for the lateral double-diffused MOS (LDMOS) with multiple floating poly-gate field plates. To reduce the worst degradation, an improved N-drift region implantation method called a partial-resist-implantation is proposed for the LDMOS. It shows that the electrical fields and impact ionization generation rates at the degradation-sensitive positions (beneath the bird’s beak and the edge of real poly-gate) have been obviously decreased. The measured data demonstrate that the degradation of on-resistance for the improved device is reduced by 13.5% after 3000 s ${\mathbf{V}}_{\mathbf{gmax}} $ stress. The charge pumping experiment has also verified the validity of the method.

Investigation of Retention Characteristics for Trap-Assisted Tunneling Mechanism in Sub 20-nm NAND Flash Memory

Abstract: In this paper, retention characteristics of the trap-assisted tunneling (TAT) mechanism are investigated in sub 20-nm NAND flash memory. Total charge loss source for the TAT mechanism ( $ {\Delta V_{\rm th({\mathrm{ TAT}})}}$ ) becomes larger with baking temperature, while the source for the detrapping mechanism is almost constant. This temperature dependence of the TAT mechanism becomes larger as program/erase cycling stress increases. Also, this trend is much larger in the highest programmed threshold voltage distribution state. By comparing activation energies of the TAT and the detrapping mechanisms, it was found that the TAT mechanism is very affected by trap density as well as the strength of the electric field in the tunneling oxide layer. To scale down, lifetime of the device can be rapidly reduced due to the decreased time-constant ( ${\tau }$ ) of the TAT mechanism.

Electromigration Failure Time Model of General Circuit-Like Interconnects

Abstract: The majority of interconnects in an integrated circuit is composed of via-terminated segments that are connected to atomic sinks or reservoirs. In this paper, we investigate electromigration failure of Cu/low-k conductors with active (current carrying) sinks and reservoirs, as well as configurations where currents flow into or out of a common via. We show that when steady-state stress profiles are combined with current densities, an accurate picture of electromigration failure for circuit-like interconnects emerges. Voiding locations are in general dependent on length and current ratios between active and sink/reservoir segments, leading to a rich variety of voiding behavior. A modeling methodology is developed to predict both voiding locations and failure time distributions in the presence of arbitrary configurations of active sinks, reservoirs, and common vias.

Reliability and Failure Analysis of UHF RFID Passive Tags Under Thermal Storage

Abstract: This paper proposes studying the effects of thermal storage on the reliability of passive ultra-high frequency radio-frequency identification tags. Two types of tags M1 and M2 from two different manufacturers are aged under two high temperatures equal to 408 K and 433 K. Tested tags are put into thermal storage oven hang fixed terms. The performances of these tags are measured after each aging phase to determine the power loss caused by high-temperature storage. Then, a mathematical approach is used to estimate for both tags from the two manufacturers the law of reliability under nominal conditions. Statistical and physical analyses of the results allow us to study and analyze the mechanisms of aging. It is observed that the failure mechanisms depend on the type of passive tags and the values of selected storage temperatures for the tests. The scale parameters of M1 tags aged at 408 K are around 280 h, whereas the scale parameters of the M2 tags aged at the same temperature are around 360 h. Cracks on the antenna are observed with the higher temperature equal to 433 K for M1 tags. However, the changes of the performance of others tags are probably caused by changes in the matching of the impedance between the antenna and the radio-frequency integrated circuit. From this study, various failure mechanisms demonstrate the necessity of determining the type of passive tags and the used temperature.