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Paul A. Merolla

Researcher at IBM

Publications -  82
Citations -  9106

Paul A. Merolla is an academic researcher from IBM. The author has contributed to research in topics: Neuromorphic engineering & TrueNorth. The author has an hindex of 25, co-authored 82 publications receiving 7298 citations. Previous affiliations of Paul A. Merolla include Stanford University & Oracle Corporation.

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A million spiking-neuron integrated circuit with a scalable communication network and interface

TL;DR: Inspired by the brain’s structure, an efficient, scalable, and flexible non–von Neumann architecture is developed that leverages contemporary silicon technology and is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification.
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TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

TL;DR: This work developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture, and successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition.
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Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations

TL;DR: Neurogrid as discussed by the authors is a real-time neuromorphic system for simulating large-scale neural models in real time using 16 Neurocores, including axonal arbor, synapse, dendritic tree, and soma.
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Convolutional networks for fast, energy-efficient neuromorphic computing

TL;DR: This approach allows the algorithmic power of deep learning to be merged with the efficiency of neuromorphic processors, bringing the promise of embedded, intelligent, brain-inspired computing one step closer.
Proceedings ArticleDOI

A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm

TL;DR: This work fabricated a key building block of a modular neuromorphic architecture, a neurosynaptic core, with 256 digital integrate-and-fire neurons and a 1024×256 bit SRAM crossbar memory for synapses using IBM's 45nm SOI process, leading to ultra-low active power consumption.