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Bernard Brezzo
Researcher at IBM
Publications - 34
Citations - 5401
Bernard Brezzo is an academic researcher from IBM. The author has contributed to research in topics: Adapter (computing) & Field-programmable gate array. The author has an hindex of 17, co-authored 34 publications receiving 4160 citations.
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Journal ArticleDOI
A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A. Merolla,John V. Arthur,Rodrigo Alvarez-Icaza,Andrew S. Cassidy,Jun Sawada,Filipp Akopyan,Bryan L. Jackson,Nabil Imam,Chen Guo,Yutaka Nakamura,Bernard Brezzo,Ivan Vo,Steven K. Esser,Rathinakumar Appuswamy,Brian Taba,Arnon Amir,Myron D. Flickner,William P. Risk,Rajit Manohar,Dharmendra S. Modha +19 more
TL;DR: Inspired by the brain’s structure, an efficient, scalable, and flexible non–von Neumann architecture is developed that leverages contemporary silicon technology and is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification.
Journal ArticleDOI
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Filipp Akopyan,Jun Sawada,Andrew S. Cassidy,Rodrigo Alvarez-Icaza,John V. Arthur,Paul A. Merolla,Nabil Imam,Yutaka Nakamura,Pallab Datta,Gi-Joon Nam,Brian Taba,Michael P. Beakes,Bernard Brezzo,Jente B. Kuang,Rajit Manohar,William P. Risk,Bryan L. Jackson,Dharmendra S. Modha +17 more
TL;DR: This work developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture, and successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition.
Proceedings ArticleDOI
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Jae-sun Seo,Bernard Brezzo,Yong Liu,Benjamin D. Parker,Steven K. Esser,Robert K. Montoye,Bipin Rajendran,Jose A. Tierno,Leland Chang,Dharmendra S. Modha,Daniel J. Friedman +10 more
TL;DR: A new architecture is proposed to overcome scalable learning algorithms for networks of spiking neurons in silicon by combining innovations in computation, memory, and communication to leverage robust digital neuron circuits and novel transposable SRAM arrays.
Proceedings ArticleDOI
Database analytics acceleration using FPGAs
Bharat Sukhwani,Hong Min,Mathew S. Thoennes,Parijat Dube,Balakrishna R. Iyer,Bernard Brezzo,Donna N. Dillenberger,Sameh W. Asaad +7 more
TL;DR: This paper presents a Field Programmable Gate Array (FPGA) based acceleration engine for database operations in analytics queries that provides a mechanism for a DBMS to seamlessly harness the FPGA compute power without requiring any changes in the application or the existing data layout.
Proceedings ArticleDOI
Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with ~100× speedup in time-to-solution and ~100,000× reduction in energy-to-solution
Andrew S. Cassidy,Rodrigo Alvarez-Icaza,Filipp Akopyan,Jun Sawada,John V. Arthur,Paul A. Merolla,Pallab Datta,Marc Gonzalez Tallada,Brian Taba,Alexander Andreopoulos,Arnon Amir,Steven K. Esser,Jeff Kusnitz,Rathinakumar Appuswamy,C. Haymes,Bernard Brezzo,Roger Moussalli,Ralph Bellofatto,Christian W. Baks,Michael Mastro,Kai Schleupen,Charles Edwin Cox,Ken Inoue,Steve Millman,Nabil Imam,Emmett McQuinn,Yutaka Nakamura,Ivan Vo,Chen Guok,Don Nguyen,Scott Lekuch,Sameh W. Asaad,Daniel Friedman,Bryan L. Jackson,Myron D. Flickner,William P. Risk,Rajit Manohar,Dharmendra S. Modha +37 more
TL;DR: True North is a 4,096 core, 1 million neuron, and 256 million synapse brain-inspired neurosynaptic processor, that consumes 65mW of power running at real-time and delivers performance of 46 Giga-Synaptic OPS/Watt.