Showing papers by "Paul S. Ho published in 2003"

Packaging effects on reliability of Cu/low-k interconnects

Abstract: Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire/spl acute/ interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.

Thermal stress characteristics of Cu/oxide and Cu/low-k submicron interconnect structures

Abstract: Thermal stress characteristics of single damascene Cu lines passivated with tetraethyl orthosilicate oxide and methyl silsesquioxane low-k dielectrics were investigated by x-ray diffraction method and finite element analysis. Lines with different aspect ratios were studied, and the effect of line geometry was evaluated. The stress characteristics of low-k passivated Cu lines indicate that the diffusion barrier plays an important role in controlling the stress behavior in damascene structure. The effect of material properties, process conditions, and interconnect structure were examined and the implications in Cu/low-k interconnect reliability are discussed.

Low Dielectric Constant Materials for IC Applications

Abstract: 1 Overview on Low Dielectric Constant Materials for IC Applications.- 1.1 Introduction.- 1.2 Dielectric Constant and Bonding Characteristics.- 1.3 Material Properties and Integration Requirements.- 1.4 Characterization of Low-? Dielectrics.- 1.5 Porous Low-? Materials.- 1.6 Conclusion.- References.- 2 Materials Issues and Characterization of Low-? Dielectric Materials.- 2.1 Introduction.- 2.2 Thin-Film Material Characterization.- 2.3 General Structure-Property Relationships.- 2.3.1 Dielectric Constant.- 2.3.2 Thermal Properties.- 2.3.3 Moisture Uptake.- 2.3.4 Thermomechanical and Thermal Stress Properties.- 2.4 Fluorinated Polyimide: Effect of Chemical-Structure Modifications on Film Properties.- 2.5 Crosslinked and Thermosetting Materials.- 2.6 Parylene Polymers: Effect of Thermal History on Film Properties.- 2.7 Future Challenges.- References.- 3 Structure and Property Characterization of Low-? Dielectric Porous Thin Films Determined by X-Ray Reflectivity and Small-Angle Neutron Scattering.- 3.1 Introduction.- 3.2 Two-Phase Methodology.- 3.2.1 Experimental.- 3.2.2 Two-Phase Analysis Using the Debye Model.- 3.2.3 Results and Discussion.- 3.3 Three-Phase Methodology.- 3.4 Films with Ordered Porous Structure.- 3.5 Limits of SANS Characterization Methods.- 3.6 Future Developments.- 3.6.1 Contrast Variation SXR.- 3.6.2 Inhomogeneous Wall Composition.- 3.7 Conclusion.- References.- 4 Vapor Deposition of Low-? Polymeric Dielectrics.- 4.1 Introduction.- 4.2 Vapor-Phase Deposition and Polymerization on Substrates.- 4.3 Parylenes.- 4.3.1 Synthesis Review.- 4.3.2 Properties of Parylene-N.- 4.3.3 Mechanisms and Models of Parylene Polymerization.- 4.3.4 Integration Issues with Parylene-N.- 4.3.5 Synthesis and Properties of Parylene-F.- 4.3.6 Integration Issues with Parylene-F.- 4.4 Polynaphthalene and Its Derivatives.- 4.4.1 Experimental System for Polynaphthalene Synthesis.- 4.4.2 Properties of Polynaphthalene and Fluorinated Polynaphthalene.- 4.5 Teflon and Its Derivatives.- 4.5.1 Synthesis of Teflon-AF.- 4.5.2 Properties of Teflon-AF.- 4.5.3 Integration Issues with Teflon.- 4.6 Vapor-Deposited Polyimides.- 4.7 Prospects for Vapor-Depositable Low-? Polymers.- References.- 5 Plasma-Enhanced Chemical Vapor Deposition of FSG and a-C:F Low-? Materials.- 5.1 Introduction.- 5.2 FSG Films.- 5.2.1 Introduction.- 5.2.2 General Characteristics.- 5.2.3 HDP-CVD FSG Film.- 5.3 a-C:F Films.- 5.3.1 Introduction.- 5.3.2 Deposition of a-C:F by PE-CVD and Controlling Fluorine Concentration.- 5.3.3 Control of F/C Ratio by Helicon-Wave HDP-CVD.- 5.3.4 Mechanism of the Reduction of the Dielectric Constant of a-C:F.- 5.3.5 Signal-Delay Measurements of CMOS Circuits.- 5.3.6 Conclusion.- References.- 6 Porous Organosilicates for On-Chip Applications: Dielectric Generational Extendibility by the Introduction of Porosity.- 6.1 Introduction.- 6.2 Porous Silica.- 6.3 Organosilicates.- 6.4 Porogens.- 6.5 Porous Organosilicate Matrix Resins.- 6.6 Formation of Nanohybrids.- 6.7 Porous Organosilicates.- 6.8 Characterization of Porous Organosilicates.- 6.9 Conclusion.- References.- 7 Metal/Polymer Interfacial Interactions.- 7.1 Introduction.- 7.2 Experimental Methods.- 7.2.1 XPS and AES Analysis.- 7.2.2 XPS for Nucleation Modes.- 7.2.3 Other Surface-Science Techniques.- 7.2.4 Metal-Deposition Techniques.- 7.3 Metallization of Fluoropolymers.- 7.3.1 Metal Evaporation.- 7.3.2 Sputter Deposition.- 7.3.3 Aluminum MOCVD.- 7.3.4 Copper MOCVD.- 7.4 Polymers on Metals: Adhesion to Cu.- 7.4.1 Introduction to SiC films.- 7.4.2 Vinyl Silane-Derived Films on Cu.- 7.5 Conclusion.- References.- 8 Diffusion of Metals in Polymers and During Metal/Polymer Interface Formation.- 8.1 Introduction.- 8.2 Thermodynamic Considerations.- 8.3 Effect of Metal-Polymer Interaction on the Mobility of Metal Atoms.- 8.4 Surface Diffusion, Nucleation, and Growth of Metal Films.- 8.5 Diffusion and Aggregation.- 8.6 Atomic Diffusion.- 8.7 Conclusion.- References.- 9 Plasma Etching of Low Dielectric Constant Materials.- 9.1 Introduction.- 9.2 Technological Requirements and Patterning Approaches.- 9.2.1 Damascene Processing.- 9.2.2 Plasma Etching.- 9.2.3 Important Low Dielectric Constant Materials.- 9.3 Fluorocarbon-Based Etching Processes.- 9.3.1 Fluorine-Doped SiO2(SiOF), Hydrogen Silsequioxane (HSQ) and Methyl Silsequioxane (MSQ).- 9.3.2 Porous Silica Films.- 9.4 Directional Etching of Organic Low-? Materials.- 9.4.1 Hydrocarbon-Based Organic Materials: Etching of Olyarylene Ether (PAE-2) in Ar/O2/N2Gas Mixtures..- 9.4.2 Fluorocarbon-Based Organic Materials: Polytetrafluoroethylene.- 9.4.3 Hybrid Materials.- 9.5 Postetch Mask-Stripping and Via-Cleaning Processes.- 9.6 Conclusion.- References.- 10 Integration of SiLK Semiconductor Dielectric.- 10.1 Introduction.- 10.2 SiLK Semiconductor Dielectric.- 10.3 Subtractive Technologies.- 10.3.1 Introduction.- 10.3.2 Integration Flow for Subtractive Interconnects.- 10.3.3 Integration Unit Steps.- 10.3.4 Electrical Results.- 10.3.5 Conclusion.- 10.4 Damascene Technologies.- 10.4.1 Introduction.- 10.4.2 Embedded-Hardmask Approach for Dual Damascene.- 10.4.3 Dual Damascene Schemes with Multilayered Hardmasks.- 10.5 Cost-of-Ownership.- 10.6 Conclusion.- References.

Electromigration reliability of dual-damascene Cu/porous methylsilsesquioxane low k interconnects

Abstract: Electromigration (EM) reliability was investigated for Cu/porous low k interconnects. The porous low k dielectric was a methylsilsesquioxane (MSQ) based spin-on organosilicate material with k of 2.2. The activation energy for EM failure was found to be about 0.9 eV for Cu/porous MSQ between 208 and 367 °C, which is commonly associated with mass transport at the Cu/SiNx cap-layer interface. The threshold product of current density and line length (jL)c for Cu/porous MSQ was found to be 2500–3000 A/cm. The reduction in EM lifetime compared with Cu/oxide interconnect can be attributed to smaller back stress, due to less thermomechanical confinement of Cu/low k interconnects. Most interconnects failed by voiding at the cathode. Some lateral Cu extrusion followed by interfacial breakdown was also observed near the anode.

Effect of packaging on interfacial cracking in Cu/ low k Damascene structures

Abstract: In this study, 3D f~te element analysis (FEA) based on a multilevel sub-modeling approach in combination with highresolution moire interferometry was employed to examine the packaging effect on low k interconnect reliability. First, 3D FEA was used to analyze the thermal deformation for a flip chip package and verified with high-resolution moire interferometry. Then multi-level sub-modeling was conducted one level of detail at a time, fust selected a section of the package around solder bumps with highest deformation, then proceeded to the die-solder interface and fmally reached the interconnect level. A crack was introduced along interested interfaces in the interconnect structures and strain energy release rate was calculated by using modified virtual crack closure technique. The FEA results will be compared with that for a stand-alone wafer structure. Both AI and Cu sttuctures were investigated and are compared. Our research results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures. Results from studies on the effects of line pitch, ILD materials, and solder bump materials will be reported and discussed. effect of packaging on the en& release rate diving interfacial delamination and its impact on reliability for Cdlow k structures. To investigate this problem, we employed 3D fmite element analysis (FEA) based on a multilevel sub-modeling approach in combmation with high-resolution moire interferometry to examine the packaging effect on low k interconnect reliability. First, 3D FEA was used to analyze the thermal deformation for a flipchip package. Here the modeling results were verified using thermal deformation and strain distributions measured by high-resolution moire interferometry. With a phase-shift technique, the resolution of moue interferometry can reach 26nm per fringe order, which is sufficient to determine strain distributions within a small area in the package accurately. After verifying FEA at the packaging level, multi-level sub-modeling was conducted one level of detail at a time, fmt selected a section of the package around solder bumps with highest deformation, then proceeded to the die-solder interface and finally reached the interconnect level. Simulation details and problems related to sub-modeling will be presented and discussed. In the submodel at the interconnect level, a crack with fvred length was introduced at relevant interfaces. The modified virtual crack

Electromigration threshold for Cu/low k interconnects

Abstract: Electromigration (EM) statistics and critical current-density line-length product (jL)/sub c/ were investigated for Cu interconnects integrated with oxide, CVD low k, porous MSQ, organic polymer dielectrics. The EM activation energy was found to be about 0.8 to 1.0 eV, which is commonly associated with mass transport at the Cu/SiN/sub x/ cap-layer interface. The lower EM lifetime and threshold product (jL)/sub c/ can be attributed to a smaller back stress due to less thermomechanical confinement in the low k structures. The confinement effect can be expressed in terms of an effective modulus B to account for EM behavior and threshold products of low k structures. For all the ILDs studied, (jL)/sub c/ showed no temperature dependence but for the organic polymer, j dependence was observed.

Impact of low k dielectrics on electromigration reliability for Cu interconnects

Abstract: Multi-link statistical test structures were used to study the effect of low k dielectrics on EM reliability of Cu interconnects. Experiments were performed on dual-damascen e Cu interconnects integrated with oxide, CVD low k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport is dominated by diffusion at the Cu/SiNx cap-layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)c observed for low-k structures can be attributed to less dielectric confinement in the low k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM. For all the ILDs studied, (jL)c showed no temperature dependence.

Characterization of low dielectric constant materials

Abstract: Publisher Summary This chapter highlights that as the integrated circuit dimensions continue to decrease, resistive–capacitative (RC) delay, crosstalk noise, and power dissipation of the interconnect structure becomes the limiting factors for ultra-large-scale integration of integrated circuits. Materials with low dielectric constant are being developed to replace silicon dioxide as inter level dielectrics. This chapter discusses the general approach to reduce the dielectric constant, emphasizing the correlation of dielectric polarizability with bonding characteristics and the tradeoff of dielectric constant and mechanical properties. It then describes the material characterization techniques, including several recently developed techniques for porous low-materials. The techniques have been applied extensively to evaluate the properties of low-dielectrics. Characteristics of three classes of materials are summarized in this chapter—polymers, silsesquioxianes, and porous dielectrics, focusing on the correlation of molecular structure and material properties. Results from porous organosilicate films reveal that dielectric constant and thermal conductivity scale with the average density of the material, the thermomechanical properties degrade significantly beyond the percolation point when the pores becomes interconnected. This points out the challenge for the development of porous low-dielectric.

Effects of passivation layer on stress relaxation in Cu line structures

Abstract: In this study, we investigate the effect of passivation layer on mass transport by measuring stress relaxation in Cu damascene line structures. SiC and SiN/sub x/ passivation layers are investigated and compared with no passivation to examine the bonding effect on mass transport. The observed stress relaxation behavior is analyzed by a kinetic model considering the contribution to mass transport via various diffusion paths including the passivation interface. Results of this study show a significant effect due to the passivation layer that can be attributed to the interfacial chemistry.

Thermal stress characteristics of two-level Al(Cu) interconnect structure

Abstract: Thermal stress characteristics of single-level and two-level Al(Cu) interconnects passivated with tetraethyl orthosilicate oxide were measured using x-ray diffraction. Thermal stresses of the second-level metal lines were deduced from the experimental data based on an analysis of the x-ray absorption in a two-level interconnect structure. The confinement effect from the substrate on the stress characteristics of metal lines at different interconnect levels was investigated. Thermal stress behavior of the second-level lines indicated that the confinement effect from the Si substrate is reduced compared to the single-level lines, resulting in reduced levels of hydrostatic and shear stresses.

Wheatstone bridge method for electromigration study of solder balls in flip-chip packages

Abstract: In this paper, we describe a new approach and a new system developed for EM tests of solder balls in a packaging assembly. The approach was based on the Wheatstone bridge method, which provided significant improvement in the sensitivity for detecting EM damage in solder balls. In the bridge circuit, each of the arms can contain an ensemble of solder balls connected in series and/or in parallel to increase the number of solder balls being tested. Thus the method can be used for EM tests of a large ensemble of solder balls, extending the range of statistical detection of early failures and reducing EM test time. Using this method, EM tests were performed at 165/spl deg/ and 235/spl deg/C on 97Pb-3Sn solder balls in ceramic flip-chip packages. The results yielded an activation energy of 0.85 eV. By extending the test time to 2000 hrs at 165/spl deg/C, all of the test circuits except one showed resistance saturation, suggesting the existence of a threshold jL/sub c/ product. Subjected to a maximum resistance change of about 15 m/spl Omega/, the jL/sub c/ product was estimated to be 110 A-cm for 97Pb-3Sn solders at 165/spl deg/C.

Wheatstone bridge method for electromigration study of solder balls in flip-chip packages

Abstract: In this paper, we describe a new approach and a new system developed for EM tests of solder balls in a packaging assembly. The approach was based on the Wheatstone bridge method, which provided significant improvement in the sensitivity for detecting EM damage in solder balls. In the bridge circuit, each of the arms can contain an ensemble of solder balls connected in series and/or in parallel to increase the number of solder balls being tested. Thus the method can be used for EM tests of a large ensemble of solder balls, extending the range of statistical detection of early failures and reducing EM test time. Using this method, EM tests were performed at 165/spl deg/ and 235/spl deg/C on 97Pb-3Sn solder balls in ceramic flip-chip packages. The results yielded an activation energy of 0.85 eV. By extending the test time to 2000 hrs at 165/spl deg/C, all of the test circuits except one showed resistance saturation, suggesting the existence of a threshold jL/sub c/ product. Subjected to a maximum resistance change of about 15 m/spl Omega/, the jL/sub c/ product was estimated to be 110 A-cm for 97Pb-3Sn solders at 165/spl deg/C.

Impact of Low k Dielectrics on Electromigration Reliability for Cu Interconnects

Abstract: Multi‐link statistical test structures were used to study the effect of low k dielectrics on EM reliability of Cu interconnects. Experiments were performed on dual‐damascene Cu interconnects integrated with oxide, CVD low k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport is dominated by diffusion at the Cu/SiNx cap‐layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)c observed for low‐k structures can be attributed to less dielectric confinement in the low k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM. For all the ILDs studied, (jL)c showed no temperature dependence.

Electromigration study of Cu dual-damascene interconnects with a CVD MSQ low k dielectric

Abstract: Electromigration reliability in Cu dual-damascene interconnects with a CVD MSQ low k dielectric was investigated. Statistical studies were carried out using the critical length (LC) test structures containing multi-link line/via elements with varying line lengths. EM lifetime characteristics, critical current density-length product (jL)c, and failure mechanisms were discussed and compared with Cu/oxide structures. Our results suggested that the diffusion at the cap layer interface was the dominant mechanism for EM mass transport. The confinement effect, in terms of an effective modulus B, can be used to account for the shorter EM lifetime and smaller critical current density-length product (jL)c observed for Cu/CVD MSQ low k interconnects. Failure analysis by FIB confirmed the presence of multiple failure modes including voiding at the via bottom, Cu extrusion and delamination at Cu/cap layer interface.