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Paul S. Ho

Researcher at University of Texas at Austin

Publications -  481
Citations -  14016

Paul S. Ho is an academic researcher from University of Texas at Austin. The author has contributed to research in topics: Electromigration & Dielectric. The author has an hindex of 60, co-authored 475 publications receiving 13444 citations. Previous affiliations of Paul S. Ho include National Institute of Standards and Technology & IBM.

Papers
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Proceedings ArticleDOI

Characterization of thermal stresses and plasticity in through-silicon via structures for three-dimensional integration

TL;DR: In this article, the thermal stress in the TSV structure was measured by the wafer curvature method and its unique stress characteristics were compared to that of a Cu thin film structure, and the importance and implication of the local plasticity and residual stress on TSV reliabilities were discussed for TSV extrusion and device keep-out zone (KOZ).
Proceedings ArticleDOI

In‐situ, high temperature x‐ray stress determination in patterned, passivated Al interconnects

TL;DR: In this article, a technique for the fast determination of stress in Al thin films in the presence of SiO2 passivation or line patterning was developed and used to investigate triaxial and biaxial stress states.
Proceedings ArticleDOI

Characterization of Viscoelasticity of Molding Compounds in Time Domain

TL;DR: In this paper, stress relaxation experiments were performed on a molding compound in the time domain and Prony series expansion was used to express the material's relaxation behavior, and a Thermo-rheologically simple model was assumed to deduce the master curve of relaxation modulus using the timetemperature equivalence assumption.
Journal ArticleDOI

How low-energy ions can enhance depositions on low-K dielectrics

TL;DR: In this article, the authors examined how low-energy ions change the chemical composition at and near their interface and found that the amount of chemical binding between the titanium nitride and dielectric is increased when low energy ions are used.
Patent

Methods of fabricating silicon nanowires and devices containing silicon nanowires

TL;DR: In this article, a method of fabricating a silicon nanowire having a width of 100 nm or less by depositing a metal film on a silicon-containing layer, treating the metal film using a wet process to produce an interconnected metal network having gaps on the silicon containing layer, and etching the siliconcontaining layer with a metal-assisted etching process to form a silicon nano-wires having width of 50 nm or more.