P
Pinjala Damaruganath
Researcher at Agency for Science, Technology and Research
Publications - 14
Citations - 223
Pinjala Damaruganath is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: Wafer & Wafer-level packaging. The author has an hindex of 7, co-authored 14 publications receiving 206 citations. Previous affiliations of Pinjala Damaruganath include Hong Kong University of Science and Technology.
Papers
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Proceedings ArticleDOI
TSV interposer fabrication for 3D IC packaging
Vempati Srinivasa Rao,Ho Soon Wee,Lee Wen Sheng Vincent,Li Hong Yu,Liao Ebin,Ranganathan Nagarajan,Chai Tai Chong,Xiaowu Zhang,Pinjala Damaruganath +8 more
TL;DR: In this article, through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented, where the TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing.
Journal ArticleDOI
Development of Large Die Fine-Pitch Cu/Low- $k$ FCBGA Package With Through Silicon via (TSV) Interposer
Tai Chong Chai,Xiaowu Zhang,John H. Lau,C. S. Selvanayagam,Pinjala Damaruganath,Yen Yi Germaine Hoe,Yue Ying Ong,Vempati Srinivasa Rao,Eva Wai,Hong Yu Li,Ebin Liao,Nagarajan Ranganathan,Kripesh Vaidyanathan,Shiguo Liu,Jiangyan Sun,M Ravi,C. J. Vath,Y Tsutsumi +17 more
TL;DR: In this paper, the TSV interposer was used for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package.
Proceedings ArticleDOI
Effect of TSV interposer on the thermal performance of FCBGA package
Yen Yi Germaine Hoe,Tang Gong Yue,Pinjala Damaruganath,Chai Tai Chong,John H. Lau,Zhang Xiaowu,Kripesh Vaidyanathan +6 more
TL;DR: In this article, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of a TSV interposer and its effect on the thermal performance of the package have been elaborated.
Proceedings ArticleDOI
Assembly and reliability of micro-bumped chips with Through-silicon Vias (TSV) interposer
Yue Ying Ong,Tai Chong Chai,Daquan Yu,Meei Leng Thew,Eipa Myo,Leong Ching Wai,Ming Chinq Jong,Vempati Srinivasa Rao,Nandar Su,Xiaowu Zhang,Pinjala Damaruganath +10 more
TL;DR: In this paper, the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × 10mm2 micro-bumped chips were presented.
Proceedings ArticleDOI
Effects of TSV (Through Silicon Via) interposer/chip on the thermal performances of 3D IC packaging
John H. Lau,Gong Yue Tang,Germaine Yen Yi Hoe,Xiaowu Zhang,Tai Chong Chai,Pinjala Damaruganath,Kripesh Vaidyanathan +6 more
TL;DR: In this article, the performance of 3D SiP with TSV (through silicon via) interposer/chip is investigated based on heat-transfer CFD (computational fluid dynamic) analyses.