P
Pramod Kumar Tiwari
Researcher at Indian Institute of Technology Patna
Publications - 140
Citations - 1240
Pramod Kumar Tiwari is an academic researcher from Indian Institute of Technology Patna. The author has contributed to research in topics: MOSFET & Subthreshold conduction. The author has an hindex of 18, co-authored 125 publications receiving 968 citations. Previous affiliations of Pramod Kumar Tiwari include Jiwaji University & National Institute of Technology, Rourkela.
Papers
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Proceedings ArticleDOI
A performance analysis of Hetero- Dielectric Dual-Material-Gate silicon-on-insulator tunnel field effect transistors (HD-DMG SOI TFETs)
TL;DR: In this paper, an investigation into the performance of Hetero-Dielectric Dual-Material Gate SOI Tunnel FET (HD-DMG SOI TFET) by varying the work functions of both tunnel and auxiliary gates and analysing its influence on the transfer characteristics and the threshold voltage is done.
Journal ArticleDOI
An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control
TL;DR: An analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field effect transistors (MOSFETs) is presented in this paper.
Proceedings ArticleDOI
Machine Learning Based Device Simulation Using Multi-variable Non-linear Regression to Assess the Impact of Device Parameter Variability on Threshold Voltage of Double Gate-All-Around (DGAA) MOSFET
TL;DR: In this paper, a machine learning approach is proposed for the analysis of device parameter variability impact on the threshold voltage of silicon-nanotube-based double gate-all-around (DGAA) MOSFET using multi-variable non-linear regression with five input variables.
Proceedings ArticleDOI
An analytical surface potential modeling of fully-depleted symmetrical double-gate (DG) strained-Si MOSFETs including the effect of interface charges
TL;DR: In this paper, a 2D surface potential model for a symmetrical double-gate strained Si MOSFET with oxide interface charges is proposed, which incorporates the effect of both positive and negative interface charges.
Journal ArticleDOI
Optimization of the properties of MOVPE-grown GaP epitaxial layers on GaP (1 1 1)B substrates
T. K. Sharma,V. K. Dixit,Tapas Ganguli,S D Singh,S. Porwal,Rajesh Kumar,Pramod Kumar Tiwari,Ashish Kumar Nath +7 more
TL;DR: In this paper, the growth temperature, low growth rate and an optimum value of the V/III ratio were optimized to obtain a mirror finish surface morphology for an epitaxial layer grown ≥820 °C under a stereo-zoom microscope.