R
R.L. Franch
Researcher at IBM
Publications - 40
Citations - 1109
R.L. Franch is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Dram. The author has an hindex of 18, co-authored 39 publications receiving 1094 citations.
Papers
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Journal ArticleDOI
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
Terry I. Chappell,B.A. Chappell,Stanley E. Schuster,J.W. Allan,S.P. Klepner,Rajiv V. Joshi,R.L. Franch +6 more
TL;DR: In this article, the authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations.
Proceedings ArticleDOI
A 4.6GHz resonant global clock distribution network
TL;DR: A resonant global clock-distribution network operating at 4.6GHz is designed in a 90nm 1.0V CMOS technology with a set of on-chip spiral inductors that resonate with the clock capacitance, resulting in 20% recycling of global clock power.
Proceedings ArticleDOI
On-chip timing uncertainty measurements on IBM microprocessors
R.L. Franch,Phillip J. Restle,Norman Karl James,William V. Huott,Joshua Friedrich,Robert Christopher Dixon,S. Weitzel,K. Van Goor,Gerard M. Salem +8 more
TL;DR: This paper describes the Skitter measurement experiences of several IBM microprocessors including PPC970MP, XBOX360TM, CELL Broadband EngineTM, and POWER6TM micro Processors running different workloads.
Journal ArticleDOI
A room temperature 0.1 /spl mu/m CMOS on SOI
Ghavam G. Shahidi,C.A. Anderson,B.A. Chappell,Terry I. Chappell,James H. Comfort,Bijan Davari,R.H. Dennard,R.L. Franch,P.A. McFarland,J.S. Neely,Tak H. Ning,M.R. Polcari,James D. Warnock +12 more
TL;DR: In this paper, an advanced 0.1 /spl mu/m CMOS technology on SOI was presented to minimize short channel effects, relatively thick nondepleted (0.15 /spl) SOI film, highly nonuniform channel doping and source-drain extension-halo were used.
Journal ArticleDOI
Fast CMOS ECL receivers with 100-mV worst-case sensitivity
B.A. Chappell,Terry I. Chappell,Stanley E. Schuster,H.M. Segmuller,J.W. Allan,R.L. Franch,Phillip J. Restle +6 more
TL;DR: CMOS emitter-coupled logic receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1- mu m technology.