Showing papers by "Rajiv V. Joshi published in 2003"

Design and CAD Challenges in sub-90nm CMOS Technologies

Abstract: This paper discusses design challenges of scaled CMOS circuits in sub-90nm technologies for high-performance digital applications. To continue scaling of the CMOS devices deep into sub-90nm technologies, fully depleted SOI, strained-Si on SiGe, FinFETs with double gate, and even further, three-dimensional circuits will be utilized to design high-performance circuits. We will discuss unique design aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process variations. As the scaling approaches various physical limits, new SOI design issues such as Vt modulation due to leakage, low-voltage impact ionization, and higher V/sub t,lin/ to maintain adequate V/sub t,sat/, continue to surface. With an eye towards the future, design and CAD issues related to sub-65nm device structures such as double gate FinFET will be discussed.

Low-power band-gap reference and temperature sensor circuit

Abstract: A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one μW. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit. The low-power circuits of the sensor circuit extend battery lifetime and data retention time of the cells of the at least one memory unit.

Three dimensional CMOS devices and integrated circuits

Abstract: Three dimensional devices and, integrated circuits are attractive options for overcoming barriers in device and interconnect scaling, offering an opportunity to continue the CMOS performance trend. This paper reviews the process technology and associated design issues in three dimensional devices and integrated circuits.

Oxide breakdown model and its impact on SRAM cell functionality

Abstract: The influence of the oxide hard breakdown (HBD) in an SRAM cell on the performance of a circuit that includes the cell, together with the bit select circuit and sense amplifier for the read and write process of the cell, have been analyzed. The analysis of the impact of oxide HBD on this circuit has been performed through the variation of different parameters as the bitline differential voltage and the read and write delays of the cell for different levels of oxide HBD damage in the cell. The results show that oxide BD between gate and source of the NFETs of the SRAM cell seems to have more influence in the circuit performance than in other cell positions.

Method to improve cache capacity of SOI and bulk

Abstract: Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

Loadless NMOS four transistor dynamic dual Vt SRAM cell

Abstract: Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation. A method is implemented for dynamically adjusting the threshold voltages of the transistors of activated memory cells during an access operation to thereby increase the read current or performance of the accessed memory cells.

Single supply level converter

Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Metal-insulator-metal capacitor and method of fabricating same

Abstract: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.

Self-timed read and write assist and restore circuit

Abstract: A read and write assist and restore circuit for a memory device includes a first device, which is responsive to a potential on a bit line such that the potential on the bit line activates the first device. A second device is driven by the first device such that when the first device is activated, a change in the bit line potential is reinforced with positive feedback by the second device during a wordline active period to enable write-back of data lost as a result of threshold voltage fluctuations in memory cell transistors coupled to the bit line.

Coupled body contacts for SOI differential circuits

Abstract: A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS Most field effect transistors (FETs) do not have body contacts FETs otherwise exhibiting a sensitivity to history effects have body contacts The body contact for each such FET is connected to at least one other body contact A back bias voltage may be provided to selected FETs

High performance dual-stage sense amplifier circuit

Abstract: A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.

Self timed bit and read/write pulse stretchers

Abstract: Bit and write decode/drivers, a random access memory (RAM) including the decode/drivers and an IC with a static RAM (SRAM) including the decode/drivers. The decode/drivers are clocked by a local clock and each produce access pulses wider than corresponding clock pulses. The bit decode/driver produces bit select pulses that are wider than a word select pulse and the write decode/driver produces write pulses that are wider than the bit select pulses for stable self timed RAM write accesses.

New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology

Abstract: This paper proposes two novel circuit techniques, one each for static and dynamic logic, for ultra-low standby sub-threshold and gate leakage power in future fully-depleted SOI technology. The proposed schemes make intelligent use/combination of SOI dual-V/sub TH/ transistors, supplementary capacitors, forced stacking and V/sub TH-/ wave-pipelining techniques to reduce power in standby mode and maintain/improve active-mode circuit speed. An analytical formula for optimum transistor sizing in the proposed dynamic logic scheme is derived and validated. It is demonstrated that the proposed schemes become very attractive for wide datapath designs in future aggressively scaled SOI technology.

Strained-Si devices and circuits for low-power applications

Abstract: Static and dynamic power for strained-Si devices are analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested by controlling physical/structural device parameters. Strained-Si CMOS circuits are studied, showing substantially-reduced power consumption due to the unique advantageous features of strained-Si devices. The trade-off between power and performance in strained-Si devices/circuits is discussed. Further, analysis and low-power design points are applied and extended to strained Si on SOI substrate (SSOI) CMOS technology.

Design of deep sub-micron CMOS circuits

Abstract: Summary form only given. Scaling down of device sizes and supply voltage requires a commensurate scaling of transistor threshold voltage to maintain high performance. Such scaling leads to exponential increase in leakage current, decreased noise immunity for high speed circuits, and increased defects. In this tutorial we present design and test techniques to combat these problems in the deep sub-micron regime for bulk, SOI and future technologies. We consider the following issues in turn: 1. Device scaling and its impact on sub-threshold and gate leakage current, interconnects, and noise immunity. 2. Low voltage circuit design under high intrinsic leakage, leakage monitoring and control techniques, effective transistor stacking, multi-threshold CMOS, dynamic threshold CMOS, SOI implications. Design of low leakage data-paths and caches. 3. SOI design - comparison with bulk, logic and memory design, asynchronous design. 4. Copper, low k, and impact of low k on performance. 5. Future technologies - double gate fully depleted SOI, FIN FET, and 3D SOI. 6. Noise modeling and analysis for high-speed precharge-evaluate circuits such as domino. Noise tolerant circuit design styles - skewed CMOS, noise tolerant domino, layout styles for high noise immunity. 7. I/sub ddq/ testing of circuits with high intrinsic leakage /sub e/lta I/sub ddq/, two parameter tests. I/sub dd/ waveform analysis.

New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology

Abstract: This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed. A new method for assigning the V/sub TH/ and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed. The optimum stacking height and tapering/sizing ratio under various design constraints are determined. Our strategies reduce MTCMOS standby leakage further by as much as 20/spl times/ and reduce virtual supply noise by 15%.

Structure and method for forming a dielectric chamber and electronic device including the dielectric chamber

Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Design considerations of scaled sub-0.1 /spl mu/m PD/SOI CMOS circuits

Abstract: This paper reviews the circuit design considerations of scaled sub-0.1 /spl mu/m partially-depleted SOI (PD/SOI) CMOS circuits for high-performance digital applications. The impact of technology/device scaling and design challenges are highlighted. Unique design aspects and issues resulting from the scaling of PD/SOI device structure, such as parasitic bipolar effect and reduced-V/sub T/ leakage, hysteretic V/sub T/ variation, low-voltage impact ionization, higher V/sub T,lin/ to maintain adequate V/sub T,sat/, scaling/thinning of Si film, gate-to-body tunneling current, self-heating, soft error rate (SER), and the introduction of strained-Si channel on SOI are addressed.

PD/SOI SRAM performance in presence of gate-to-body tunneling current

Abstract: This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.

SRAM cell with bootstrapped power line

Abstract: A memory cell includes at least one active device for selectively connecting a supply voltage node to a power line. The power line couples capacitive elements through the at least one active device to the supply voltage node to maintain a high state while accessing a storage node. The high state is provided by a boost created by the addition of the capacitive elements.